公开(公告)号：US20200002813A1

公开(公告)日：2020-01-02

申请号：US16023470

申请日：2018-06-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  John H. Zhang ,  Jinping Liu

IPC: C23C16/455

Abstract: Systems and methods for depositing a material by atomic layer deposition. A first gas distribution unit is configured to provide a first precursor to a first zone inside a reaction chamber. A second gas distribution unit is configured to provide a second precursor to a second zone inside the reaction chamber. A substrate support is arranged to hold the substrates inside the reaction chamber. The substrate support is configured to linearly move the substrates relative to the reaction chamber from the first zone to the second zone as part of a cyclic deposition cycle of an atomic layer deposition process depositing the film on each of the substrates held by the substrate support.

公开(公告)号：US20190355832A1

公开(公告)日：2019-11-21

申请号：US16523340

申请日：2019-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Chang Seo Park ,  Shimpei Yamaguchi ,  Tao Han ,  Yong Mo Yang ,  Jinping Liu ,  Hyuck Soo Yang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative IC product disclosed herein includes first and second final gate structures and an insulating gate separation structure positioned between the first and second final gate structures. In one embodiment, the insulating gate separation structure has a stepped bottom surface with a substantially horizontally oriented bottom central surface that is surrounded by a substantially horizontally oriented recessed surface, wherein the substantially horizontally oriented bottom central surface is positioned a first level above the substrate and the substantially horizontally oriented recessed surface is positioned at a second level above the substrate, wherein the second level is greater than the first level.

公开(公告)号：US10475693B1

公开(公告)日：2019-11-12

申请号：US16002403

申请日：2018-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Hong Yu ,  Jinping Liu ,  Hui Zang

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A method includes forming a first hard mask layer above a substrate. The first hard mask layer is patterned to define a plurality of fin openings and at least a first diffusion break opening. A first etch process is performed to define a plurality of fins in the substrate and a first diffusion break recess in a selected fin. A first dielectric layer is formed between the fins and in the first diffusion break recess to define a first diffusion break. A second hard mask layer having a second opening positioned above the first diffusion break is formed above the first hard mask layer and the first dielectric layer. A second dielectric layer is formed in the second opening. The second hard mask layer is removed. A second etch process is performed to recess the first dielectric layer to expose upper portions of the plurality of fins.

公开(公告)号：US10347541B1

公开(公告)日：2019-07-09

申请号：US15962808

申请日：2018-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  David Paul Brunco ,  Pei Liu ,  Shariq Siddiqui ,  Jinping Liu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08

Abstract: A method of forming contacts over active gates is provided. Embodiments include forming first and second gate structures over a portion of a fin; forming a first and second RSD in a portion of the fin between the first gate structures and between the first and the second gate structure, respectively; forming TS structures over the first and second RSD; forming a first cap layer over the first and second gate structures or over the TS structures; forming a metal oxide liner over the substrate, trenches formed; filling the trenches with a second cap layer; forming an ILD layer over the substrate; forming a CA through a first portion of the ILD and metal oxide layer down to the TS structures over the second RSD; and forming a CB through a second portion of the ILD and metal oxide layer down to the first gate structures.

公开(公告)号：US10312150B1

公开(公告)日：2019-06-04

申请号：US15919594

申请日：2018-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Fuad Al-Amoody ,  Jinping Liu ,  Joseph Kassim ,  Bharat Krishnan

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78 ,  H01L21/475 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

Abstract: Methods of forming a fin-type field-effect transistor. A gate structure is formed that extends across a plurality of semiconductor fins. A spacer layer composed of a dielectric material is conformally deposited over the gate structure, the semiconductor fins, and a dielectric layer in gaps between the semiconductor fins. A protective layer is conformally deposited over the spacer layer. The protective layer over the dielectric layer in the gaps between the semiconductor fins is masked, and the protective layer is then removed from the gate structure and the semiconductor fins selective to the dielectric material of the spacer layer.

公开(公告)号：US20190067010A1

公开(公告)日：2019-02-28

申请号：US15689668

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Jinping Liu ,  Rui Chen

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816

Abstract: Methods of multiple patterning. First and second mandrel lines are formed on a patternable layer. Sidewall spacers are formed on the patternable layer adjacent to the first mandrel line and adjacent to the second mandrel line. A portion of the first mandrel line is removed to form a gap in the first mandrel line. A gapfill material is deposited in the gap in the first mandrel line. The gapfill material and sidewall spacers are composed of the same material.

公开(公告)号：US09754837B1

公开(公告)日：2017-09-05

申请号：US15160409

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Jinping Liu ,  Huang Liu ,  Taifong Chao

IPC: H01L29/15 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/28518 ,  H01L21/31053 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7856

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a mask over an oxide layer and an underlying set of fin structures, the set of fin structures including a plurality of fins each having a substrate base and a silicide layer over the substrate base; implanting the oxide layer through an opening in the mask; removing the mask; polishing the oxide layer overlying the set of fin structures after removing the mask to expose the set of fin structures; and forming a nitride layer over the set of fin structures.

公开(公告)号：US09711447B1

公开(公告)日：2017-07-18

申请号：US15290277

申请日：2016-10-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Qiang Fang ,  Daniel W. Fisher ,  Haigou Huang ,  Jinping Liu ,  Haifeng Sheng ,  Zhiguo Sun

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/53238

Abstract: Methods of lithographic patterning and structures formed by lithographic patterning. A hardmask layer is formed on a dielectric layer, a feature is formed on the hardmask layer, and a mandrel is formed that extends in a first direction across the first feature. The mandrel and the hardmask layer beneath the mandrel are removed to pattern the hardmask layer with the feature masking a section of the hardmask layer. After the hardmask layer is patterned, the dielectric layer is etched to form a first trench and a second trench that are separated by a section of the dielectric layer masked by the section of the hardmask layer. The first trench and the second trench are filled with a conductor layer to respectively form a first wire and a second wire that is separated from the first wire by the section of the dielectric layer.

公开(公告)号：US09698018B1

公开(公告)日：2017-07-04

申请号：US15132589

申请日：2016-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Haigou Huang ,  Jinping Liu

IPC: H01L21/225 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L21/2255 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795

Abstract: A method of introducing self-aligned dopants in semiconductor fins and the resulting device are provided. Embodiments include providing semiconductor fins on first and second portions of a substrate; forming a BSG layer on side surfaces of the semiconductor fins on the first portion of the substrate; forming a first SiN layer on the BSG layer; forming a high quality oxide layer over an upper surface of the substrate, the first SiN layer and side surfaces of the semiconductor fins on the second portion of the substrate; forming a PSG layer over the high quality oxide layer on the second portion of the substrate and side surfaces of the semiconductor fins on the second portion of the substrate; and forming a second SiN layer over the high quality oxide layer and the PSG layer.

公开(公告)号：US09673301B1

公开(公告)日：2017-06-06

申请号：US15047018

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Fuad Al-Amoody ,  Jinping Liu ,  Haifeng Sheng

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/223

CPC classification number: H01L29/66795 ,  H01L21/2236 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/31155 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes forming a liner layer above a layer of spacer material, forming an ion-containing region in at least a portion of a first portion of the liner layer while not forming the ion-containing region in a second portion of the liner layer, performing a liner etching process on the first and second portions of the liner layer so as to remove the second portion of the liner layer while leaving at least a portion of the first portion of the liner layer positioned adjacent a gate structure and, with the first portion of the liner layer positioned adjacent the gate structure, performing at least one spacer formation anisotropic etching process on the layer of spacer material so as to define a spacer adjacent the gate structure.