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    Self-aligned metal wire on contact structure and method for forming same
    41.
    发明授权
    Self-aligned metal wire on contact structure and method for forming same 有权

    公开(公告)号：US10199271B1

    公开(公告)日：2019-02-05

    申请号：US15693651

    申请日：2017-09-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Guillaume Bouche ,  Laertis Economikos ,  Lei Sun ,  Guoxiang Ning ,  Xunyuan Zhang

    IPC: H01L29/45 ,  H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L23/535 ,  H01L21/285 ,  H01L23/532 ,  H01L23/528

    Abstract: A structure and method for forming a self-aligned metal wire on a contact structure. The method for forming the self-aligned metal wire and contact structure may include, among other things, forming an initial contact structure above a substrate; forming a patterned mask on the initial contact structure, the mask including an opening; using the patterned mask to form an opening through the initial contact structure; forming a dielectric layer in the openings; removing the patterned mask to expose a remaining portion of the initial contact structure; and forming the metal wire on the remaining portion of the initial contact structure. The contact structure may include a vertical cross-sectional geometry including one of a trapezoid wherein a bottommost surface of the first contact structure is wider than an uppermost surface of the first contact structure, and a parallelogram. The metal wire may completely contact an uppermost surface of the contact structure.

    Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates
    42.
    发明授权
    Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates 有权

    公开(公告)号：US10090402B1

    公开(公告)日：2018-10-02

    申请号：US15658835

    申请日：2017-07-25

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Chanro Park ,  Chang Ho Maeng ,  Pei Liu ,  Junsic Hong ,  Laertis Economikos ,  Ruilong Xie

    IPC: H01L29/66 ,  H01L29/06

    Abstract: The method includes steps for improving gate cut isolation region critical dimension (CD) control. Prior to replacement metal gate (RMG) formation, a first sacrificial gate adjacent to first and second channel regions and made of a first sacrificial material (e.g., polysilicon or amorphous silicon) is replaced with a second sacrificial gate made of a second sacrificial material (e.g., amorphous carbon) that is more selectively and anisotropically etchable. A cut is made, dividing the second sacrificial gate into first and second sections, and the cut is then filled with a dielectric to form the gate cut isolation region. The second sacrificial material ensures that, when an opening in a mask pattern used to form the cut extends over a gate sidewall spacer and interlayer dielectric (ILD) material, recesses are not form within the spacer or ILD. Thus, the CD of the isolation region can be controlled.

    Gate cut isolation formed as layer against sidewall of dummy gate mandrel
    45.
    发明授权
    Gate cut isolation formed as layer against sidewall of dummy gate mandrel 有权

    公开(公告)号：US10707206B2

    公开(公告)日：2020-07-07

    申请号：US16194691

    申请日：2018-11-19

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

    IPC: H01L27/08 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311

    Abstract: A method of forming a gate cut isolation, a related structure and IC are disclosed. The method forms a dummy gate material mandrel having a sidewall positioned between and spaced from a first active region covered by the mandrel and a second active region not covered by the mandrel. A gate cut dielectric layer is formed against the sidewall of the mandrel, and may be trimmed. A dummy gate material may deposited to encase the remaining gate cut dielectric layer. Subsequent dummy gate formation and replacement metal gate processing forms a gate conductor with the gate cut isolation electrically isolating respective first and second portions of the gate conductor. The method creates a very thin, slightly non-vertical gate cut isolation, and eliminates the need to define a gate cut critical dimension or fill a small gate cut opening.

    GATE CUT ISOLATION FORMED AS LAYER AGAINST SIDEWALL OF DUMMY GATE MANDREL
    46.
    发明申请
    GATE CUT ISOLATION FORMED AS LAYER AGAINST SIDEWALL OF DUMMY GATE MANDREL 审中-公开

    公开(公告)号：US20200161296A1

    公开(公告)日：2020-05-21

    申请号：US16194691

    申请日：2018-11-19

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

    IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

    Abstract: A method of forming a gate cut isolation, a related structure and IC are disclosed. The method forms a dummy gate material mandrel having a sidewall positioned between and spaced from a first active region covered by the mandrel and a second active region not covered by the mandrel. A gate cut dielectric layer is formed against the sidewall of the mandrel, and may be trimmed. A dummy gate material may deposited to encase the remaining gate cut dielectric layer. Subsequent dummy gate formation and replacement metal gate processing forms a gate conductor with the gate cut isolation electrically isolating respective first and second portions of the gate conductor. The method creates a very thin, slightly non-vertical gate cut isolation, and eliminates the need to define a gate cut critical dimension or fill a small gate cut opening.

    TRANSISTOR COMPRISING AN AIR GAP POSITIONED ADJACENT A GATE ELECTRODE
    48.
    发明申请
    TRANSISTOR COMPRISING AN AIR GAP POSITIONED ADJACENT A GATE ELECTRODE 审中-公开

    公开(公告)号：US20200066899A1

    公开(公告)日：2020-02-27

    申请号：US16664056

    申请日：2019-10-25

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

    IPC: H01L29/78 ,  H01L21/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

    Abstract: A transistor device disclosed herein includes, among other things, a gate electrode positioned above a semiconductor material region, a sidewall spacer positioned adjacent the gate electrode, a gate insulation layer having a first portion positioned between the gate electrode and the semiconductor material region and a second portion positioned between a lower portion of the sidewall spacer and the gate electrode along a portion of a sidewall of the gate electrode, an air gap cavity located between the sidewall spacer and the gate electrode and above the second portion of the gate insulation layer, and a gate cap layer positioned above the gate electrode, wherein the gate cap layer seals an upper end of the air gap cavity so as to define an air gap positioned adjacent the gate electrode.

    Gate cut method after source/drain metallization
    49.
    发明授权
    Gate cut method after source/drain metallization 有权

    公开(公告)号：US10566201B1

    公开(公告)日：2020-02-18

    申请号：US16174510

    申请日：2018-10-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Chanro Park ,  Ruilong Xie ,  Hui Zang ,  Laertis Economikos ,  Andre LaBonte

    IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/423 ,  H01L23/535 ,  H01L29/66

    Abstract: A method that includes forming a conductive source/drain structure that is conductively coupled to source/drain regions of first and second transistor devices, selectively forming a conductive source/drain metallization cap structure on and in contact with an upper surface of the conductive source/drain structure, forming a patterned etch mask that exposes a portion of the gate cap and a portion of the conductive source/drain metallization cap structure, and performing at least one etching process to remove the exposed portion of the gate cap and thereafter an exposed portion of the final gate structure so as to form a gate cut opening, wherein the conductive source/drain metallization cap structure protects the underlying conductive source/drain structure during the at least one etching process.

    Field effect transistors with self-aligned metal plugs and methods
    50.
    发明授权
    Field effect transistors with self-aligned metal plugs and methods 有权

    公开(公告)号：US10553486B1

    公开(公告)日：2020-02-04

    申请号：US16047037

    申请日：2018-07-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hui Zang ,  Ruilong Xie ,  Laertis Economikos

    IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/321

    Abstract: Disclosed is a method of forming an integrated circuit (IC) and the resulting structure. The method includes forming a transistor with a sacrificial gate on a channel region, a gate sidewall spacer on the sacrificial gate, and sacrificial plugs on the source/drain regions. The sacrificial gate is replaced with a gate, a gate cap on the gate, and a sacrificial cap on the gate cap and the gate sidewall spacer (which was recessed). Thus, top surfaces of the gate cap and gate sidewall spacer are at a lower level than the top surfaces of the sacrificial plugs and, when the sacrificial plugs are replaced with metal plugs, the gate cap is protected. In the resulting structure, the gate cap has a desired thickness and the top surface of the gate cap is at a lower level than the top surfaces of the metal plugs to reduce the risk of shorts.

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