公开(公告)号：US07186571B2

公开(公告)日：2007-03-06

申请号：US10769107

申请日：2004-01-30

Applicant: Heon Lee ,  Manish Sharma

Inventor： Heon Lee ,  Manish Sharma

IPC: H01L21/00

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: A magnetic tunnel junction device with a compositionally modulated electrode and a method of fabricating a magnetic tunnel junction device with a compositionally modulated electrode are disclosed. An electrode in electrical communication with a data layer of the magnetic tunnel junction device includes a high resistivity region that has a higher resistivity than the electrode. As a result, a current flowing through the electrode generates joule heating in the high resistivity region and that joule heating increases a temperature of the data layer and reduces a coercivity of the data layer. Consequently, a magnitude of a switching field required to rotate an alterable orientation of magnetization of the data layer is reduced. The high resistivity region can be fabricated using a plasma oxidation, a plasma nitridation, a plasma carburization, or an alloying process.

Abstract translation: 公开了一种具有组成调制电极的磁性隧道结器件和一种制造具有组成调制电极的磁性隧道结器件的方法。 与磁性隧道结装置的数据层电连通的电极包括具有比电极更高的电阻率的高电阻率区域。 结果，流过电极的电流在高电阻率区域产生焦耳加热，并且焦耳加热增加数据层的温度并降低数据层的矫顽力。 因此，减小了旋转数据层的磁化方向的可变方向所需的切换场的大小。 高电阻率区域可以使用等离子体氧化，等离子体氮化，等离子体渗碳或合金化工艺来制造。

公开(公告)号：US07102921B2

公开(公告)日：2006-09-05

申请号：US10843787

申请日：2004-05-11

Applicant: Thomas C. Anthony ,  Frederick A. Perner ,  Heon Lee ,  Robert G Walmsley

Inventor： Thomas C. Anthony ,  Frederick A. Perner ,  Heon Lee ,  Robert G Walmsley

IPC: G11C11/14

CPC classification number: G11C11/16 ,  G11C11/1675

Abstract: The present invention provides a magnetic memory device that includes a magnetic memory cell switchable between two states by the application of a magnetic field wherein the magnetic field for such switching is dependent in part on a memory cell temperature. The device further includes at least one heater element proximate to the magnetic memory cell and series connected with the magnetic memory cell for heating of the magnetic memory cell. The device also includes a circuit for selectively applying the electrical current through the at least one heater element so as to heat the cell and facilitate cell state-switching.

Abstract translation: 本发明提供了一种磁存储器件，其包括通过施加磁场在两个状态之间切换的磁存储器单元，其中用于这种切换的磁场部分地取决于存储单元温度。 该装置还包括靠近磁存储器单元的至少一个加热器元件，并且与磁存储单元连接的用于加热磁存储单元的串联。 该装置还包括用于选择性地施加电流通过至少一个加热器元件以便加热电池并促进电池状态切换的电路。

公开(公告)号：US06998662B2

公开(公告)日：2006-02-14

申请号：US11080092

申请日：2005-03-14

Applicant: Heon Lee

Inventor： Heon Lee

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: A method of making a magnetic tunnel junction device is disclosed. The magnetic tunnel junction device includes a magnetic tunnel junction stack and an electrically non-conductive spacer in contact with a portion of the magnetic tunnel junction stack. The spacer electrically insulates a portion of the magnetic tunnel junction stack from an electrically conductive material used for a via that is in contact with the magnetic tunnel junction stack and a top conductor. The spacer can also prevent an electrical short between a bottom conductor and the top conductor. The spacer can prevent electrical shorts when the magnetic tunnel junction stack and a self-aligned via are not aligned with each other.

Abstract translation: 公开了制造磁性隧道结装置的方法。 磁性隧道结装置包括磁性隧道结叠层和与磁性隧道结叠层的一部分接触的非导电间隔物。 间隔件将磁性隧道结堆叠的一部分与用于与磁性隧道结叠层和顶部导体接触的通路的导电材料电绝缘。 隔离器还可以防止底部导体和顶部导体之间的电短路。 当磁性隧道结堆叠和自对准通孔彼此不对齐时，间隔件可以防止电气短路。

公开(公告)号：US20060021967A1

公开(公告)日：2006-02-02

申请号：US10766710

申请日：2004-01-27

Applicant: Heon Lee

Inventor： Heon Lee

IPC: C23F1/00

CPC classification number: G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  C23F4/00

Abstract: A method of fabricating an imprint stamp is disclosed. The imprint stamp includes a plurality of layers of material that are deposited in a deposition order. After deposition, each layer is patterned and then etched to form a portion of an application specific imprint pattern. The portion includes variations in a topography of the layer. The application specific imprint pattern comprises a plurality of features that are defined by the variations in the topographies of all of the layers of material that were deposited, patterned, and etched. The imprint stamp can be used in a soft-lithography process by pressing the application specific imprint pattern into a mask layer in which the application specific imprint pattern is replicated.

Abstract translation: 公开了一种制造压印印模的方法。 压印印模包括以沉积顺序沉积的多层材料。 沉积后，对各层进行图案化，然后进行蚀刻以形成应用特定印记图案的一部分。 该部分包括该层的形貌的变化。 应用特定印记图案包括由沉积，图案化和蚀刻的所有材料层的形貌的变化所限定的多个特征。 通过将应用程序特定印记图案压入其中应用特定印记图案被复制的掩模层中，可以在软光刻工艺中使用印记印模。

公开(公告)号：US06984862B2

公开(公告)日：2006-01-10

申请号：US10689940

申请日：2003-10-20

Applicant: Hang Liao ,  Zhizhang Chen ,  Alexander Govyadinov ,  Leslie Louis Szepesi, Jr. ,  Heon Lee

Inventor： Hang Liao ,  Zhizhang Chen ,  Alexander Govyadinov ,  Leslie Louis Szepesi, Jr. ,  Heon Lee

IPC: H01L29/788

CPC classification number: B82Y10/00 ,  G11B9/08 ,  G11B9/14 ,  G11B9/1409 ,  G11B9/1418 ,  G11B9/1436 ,  G11B11/08

Abstract: A storage device includes a first semiconducting layer having a p-dopant and a second semiconducting layer having an n-dopant, disposed on the first semiconducting layer forming a junction between the first and the second semiconducting layers. The storage device also includes a charge trapping structure disposed on the second semiconducting layer and a conductive gate, wherein the conductive gate and the charge trapping structure move relative to the other, wherein an electric field applied across the second semiconducting layer and the conductive gate traps charge in the charge trapping structure.

Abstract translation: 存储装置包括具有p-掺杂剂的第一半导体层和具有n-掺杂剂的第二半导体层，其设置在第一半导体层上，形成第一和第二半导体层之间的结。 存储装置还包括设置在第二半导体层上的电荷捕获结构和导电栅极，其中导电栅极和电荷捕获结构相对于另一个迁移，其中施加在第二半导体层和导电栅极阱上的电场 电荷捕获结构中的电荷。

公开(公告)号：US20050214953A1

公开(公告)日：2005-09-29

申请号：US10811553

申请日：2004-03-29

Applicant: Heon Lee ,  Thomas Anthony ,  Manish Sharma

Inventor： Heon Lee ,  Thomas Anthony ,  Manish Sharma

IPC: H01L21/8246 ,  H01L27/22 ,  H01L43/12 ,  H01L21/336

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: A method of fabricating a magnetic random access memory (MRAM) device is disclosed. The method reduces the number of mask steps and processing steps required to fabricate the MRAM device. A first conductive layer and a sense layer are patterned in a first mask step. A subsequent etching step forms a bottom electrode and a sense layer that are continuous with each other in a first direction. A second conductive layer and a plurality of layers of material required to form a magnetic tunnel junction stack are patterned in a second mask step. A subsequent etching step forms a top electrode and a plurality of layers of material that are continuous with each other in a second direction, and a plurality of discrete sense layers. The discrete sense layers and the plurality of layers of material define a plurality of magnetic tunnel junction devices.

Abstract translation: 公开了制造磁随机存取存储器（MRAM）装置的方法。 该方法减少了制造MRAM设备所需的掩模步骤和处理步骤的数量。 第一导电层和感测层在第一掩模步骤中被图案化。 随后的蚀刻步骤形成在第一方向上彼此连续的底部电极和感测层。 在第二掩模步骤中图案化形成磁性隧道结叠层所需的第二导电层和多层材料。 随后的蚀刻步骤形成在第二方向上彼此连续的顶部电极和多个材料层，以及多个离散感测层。 离散感测层和多层材料限定了多个磁性隧道结装置。

公开(公告)号：US06900468B2

公开(公告)日：2005-05-31

申请号：US09789458

申请日：2001-02-20

Applicant: Alison Chalken ,  Gary Gibson ,  Heon Lee ,  Krysztof Nauka ,  Chung-Ching Yang

Inventor： Alison Chalken ,  Gary Gibson ,  Heon Lee ,  Krysztof Nauka ,  Chung-Ching Yang

IPC: G11B11/00 ,  G11C11/56 ,  G11C16/02 ,  H01L27/10 ,  H01L27/105 ,  H01L31/0248 ,  H01L45/00 ,  H01L27/15

CPC classification number: G11B7/2437 ,  G11B7/2433 ,  G11B2007/2431 ,  G11B2007/24316 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/04

Abstract: Ultra-high-density data-storage media employing indium chalcogenide, gallium chalcogenide, and indium-gallium chalcogenide films to form bit-storage regions that act as photoconductive, photovoltaic, or photoluminescent semiconductor devices that produce electrical signals when exposed to electromagnetic radiation, or to form bit-storage regions that act as cathodoconductive, cathodovoltaic, or cathodoluminescent semiconductor devices that produce electrical signals when exposed to electron beams. Two values of a bit are represented by two solid phases of the data-storage medium, a crystalline phase and an amorphous phase, with transition between the two phases effected by heating the bit storage region.

Abstract translation: 使用铟硫属化物，镓硫族化物和铟镓硫族化物膜的超高密度数据存储介质，以形成充当用于在暴露于电磁辐射时产生电信号的光电导，光伏或光致发光半导体器件的位存储区域;或 以形成用作当暴露于电子束时产生电信号的阴极导电，阴极伏安或阴极发光半导体器件的位存储区域。 位的两个值由数据存储介质的两个固相，晶相和非晶相表示，通过加热位存储区域而在两相之间转变。

公开(公告)号：US20050082598A1

公开(公告)日：2005-04-21

申请号：US10689940

申请日：2003-10-20

Applicant: Hang Liao ,  Zhizhang Chen ,  Alexander Govyadinov ,  Leslie Szepesi ,  Heon Lee

Inventor： Hang Liao ,  Zhizhang Chen ,  Alexander Govyadinov ,  Leslie Szepesi ,  Heon Lee

IPC: H01L29/06 ,  G11B9/00 ,  G11B9/08 ,  G11B11/08 ,  H01L27/10 ,  H01L29/788

CPC classification number: B82Y10/00 ,  G11B9/08 ,  G11B9/14 ,  G11B9/1409 ,  G11B9/1418 ,  G11B9/1436 ,  G11B11/08

Abstract: A storage device includes a first semiconducting layer having a p-dopant and a second semiconducting layer having an n-dopant, disposed on the first semiconducting layer forming a junction between the first and the second semiconducting layers. The storage device also includes a charge trapping structure disposed on the second semiconducting layer and a conductive gate, wherein the conductive gate and the charge trapping structure move relative to the other, wherein an electric field applied across the second semiconducting layer and the conductive gate traps charge in the charge trapping structure.

Abstract translation: 存储装置包括具有p-掺杂剂的第一半导体层和具有n-掺杂剂的第二半导体层，其设置在第一半导体层上，形成第一和第二半导体层之间的结。 存储装置还包括设置在第二半导体层上的电荷捕获结构和导电栅极，其中导电栅极和电荷捕获结构相对于另一个迁移，其中施加在第二半导体层和导电栅极阱上的电场 电荷捕获结构中的电荷。

公开(公告)号：US06838339B2

公开(公告)日：2005-01-04

申请号：US10456648

申请日：2003-06-05

Applicant: Heon Lee

Inventor： Heon Lee

IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC classification number: H01L28/84 ,  H01L27/10855 ,  H01L28/65 ,  H01L28/91

Abstract: An area-efficient stack capacitor for use in an integrated circuit comprises, in one embodiment, a layer of elemental platinum (Pt) as a bottom electrode, a layer of hemispherical grained poly Si on top of the Pt bottom electrode, a second layer of Pt deposited over the layer of hemispherical grained poly Si, a layer of dielectric deposited over the second layer of Pt, and a third layer of Pt deposited over the dielectric layer, where the third layer of Pt acts as upper electrode.

Abstract translation: 在一个实施例中，用于集成电路的面积有效的堆叠电容器包括作为底部电极的元素铂（Pt）层，Pt底部电极顶部的半球状晶粒多晶硅层，第二层 Pt沉积在半球状晶粒多晶硅层上，沉积在第二层Pt上的电介质层和沉积在介电层上的第三层Pt，其中第三层Pt作为上电极。

公开(公告)号：US06753252B2

公开(公告)日：2004-06-22

申请号：US09861253

申请日：2001-05-18

Applicant: Youngjin Park ,  Heon Lee ,  David E. Kotecki ,  Greg Costrini

Inventor： Youngjin Park ,  Heon Lee ,  David E. Kotecki ,  Greg Costrini

IPC: H01L2144

CPC classification number: H01L27/10855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: Methods for fabricating a semiconductor device are disclosed. Parallel gate structures are formed on a substrate with spaces between the gate structures. A blanket depositing of a conductive material is performed to fill the spaces and cover the gate structures such that contact with the substrate is made by the conductive material. A mask is patterned to remain over active area regions. The mask remains over the spaces. The conductive material is removed in accordance with the mask to provide contacts formed from the conductive material which fills the spaces over the active areas. A dielectric layer is deposited over the gate structures and over the contacts. Holes down to the contacts are formed, and a conductive region is connected to the contacts through the holes.

Abstract translation: 公开了制造半导体器件的方法。 在栅极结构之间具有间隔的基板上形成平行栅极结构。 执行导电材料的覆盖沉积以填充空间并覆盖栅极结构，使得与衬底的接触由导电材料制成。 将掩模图案化以保留在有效区域区域上。 面具保留在空间上。 根据掩模去除导电材料以提供由填充有效区域上的空间的导电材料形成的触点。 电介质层沉积在栅极结构和触点上方。 形成到触点的孔，并且通过孔将导电区域连接到触点。