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    SEMICONDUCTOR DEVICE
    41.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110140277A1

    公开(公告)日：2011-06-16

    申请号：US13030861

    申请日：2011-02-18

    申请人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

    发明人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

    IPC分类号： H01L23/522

    CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

    摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

    Semiconductor device with resistor elements formed on insulating film
    44.
    发明授权
    Semiconductor device with resistor elements formed on insulating film 有权
    具有形成在绝缘膜上的电阻元件的半导体器件

    公开(公告)号：US07045865B2

    公开(公告)日：2006-05-16

    申请号：US09960495

    申请日：2001-09-24

    申请人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

    发明人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

    IPC分类号： H01L29/76 ,  H01L29/00 ,  H01L21/20

    CPC分类号： H01L27/0207 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/20

    摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

    摘要翻译： 本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。 有源区靠近电阻元件配置。 这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。

    Modulator providing only quantization error component to delta sigma modulator
    45.
    发明授权
    Modulator providing only quantization error component to delta sigma modulator 有权
    调制器只提供量化误差分量到ΔΣ调制器

    公开(公告)号：US07009539B2

    公开(公告)日：2006-03-07

    申请号：US10715456

    申请日：2003-11-19

    申请人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

    发明人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

    IPC分类号： H03M3/00

    CPC分类号： H03M3/46 ,  H03M3/418 ,  H03M3/454 ,  H03M3/50 ,  H03M7/3022 ,  H03M7/3028 ,  H03M7/304

    摘要： A ΔΣ modulator modulates only an error component separated by a component separating portion. Therefore, even if the number of order of the ΔΣ modulator increases, an amplitude of an output of an integrator in the final stage does not excessively increase, and the stability of the modulator can be achieved. Since the signal component separated by the component separating portion does not pass through the ΔΣ modulator, an intensity of an input signal can be maintained as it is, and the modulator can have high precision.

    摘要翻译： DeltaSigma调制器仅调制由分量分离部分分离的误差分量。 因此，即使DeltaSigma调制器的次数增加，最终级的积分器的输出的幅度也不会过度增加，并且可以实现调制器的稳定性。 由于由分量分离部分分离的信号分量不通过ΔΣ调制器，所以可以保持输入信号的强度，并且调制器可以具有高精度。

    Analog/digital converter and voltage comparator capable of fast producing of output offset voltage
    46.
    发明授权
    Analog/digital converter and voltage comparator capable of fast producing of output offset voltage 失效
    模拟/数字转换器和电压比较器能够快速产生输出失调电压

    公开(公告)号：US5966088A

    公开(公告)日：1999-10-12

    申请号：US982279

    申请日：1997-12-01

    申请人： Osamu Matsumoto ,  Toshio Kumamoto

    发明人： Osamu Matsumoto ,  Toshio Kumamoto

    IPC分类号： H03M1/44 ,  H03M1/10 ,  H03M1/16

    CPC分类号： H03M1/1023 ,  H03M1/168

    摘要： An A/D converter includes a sample-hold circuit, A/D converting stages connected in series to the sample-hold circuit, and an encoder/latch circuit which adds 3-bit digital signals issued from the A/D converting stages to each other for outputting a signal of 9 bits. The sample-hold circuit and the A/D converting stages each include a differential amplifier. Differential outputs of each differential amplifier are short-circuited for a predetermined initial period in each sampling period.

    摘要翻译： A / D转换器包括采样保持电路，与采样保持电路串联连接的A / D转换级，以及编码器/锁存电路，其将从A / D转换级发出的3位数字信号加到每个 另一个用于输出9位的信号。 采样保持电路和A / D转换级各自包括差分放大器。 在每个采样周期中，每个差分放大器的差分输出在预定的初始周期短路。

    Voltage comparator and pipeline type A/D converter
    47.
    发明授权
    Voltage comparator and pipeline type A/D converter 失效
    电压比较器和流水线型A / D转换器

    公开(公告)号：US5696511A

    公开(公告)日：1997-12-09

    申请号：US738585

    申请日：1996-10-29

    申请人： Osamu Matsumoto ,  Toshio Kumamoto

    发明人： Osamu Matsumoto ,  Toshio Kumamoto

    IPC分类号： H03M1/10 ,  H03F3/45 ,  H03M1/06 ,  H03M1/12 ,  H03M1/14 ,  H03M1/16 ,  H03M1/42

    CPC分类号： H03M1/0695 ,  H03M1/167

    摘要： In a pipeline type A/D converter, a sample/hold.cndot.subtracter circuit of an A/D converter block of a first stage samples an analog voltage and outputs an offset voltage at a first phase, and subtracts an output voltage of an A/D converter from the sampled analog voltage in a second phase. An A/D converter of an A/D converter block of a succeeding stage subtracts the output voltage of the sample/hold.cndot.subtracter circuit of the first phase from the output voltage of the sample hold.cndot.subtracter circuit of the second phase, and converts the subtracted result into a digital code. The influence of an offset of a differential amplifier included in the sample/hold.cndot.subtracter circuit is removed so that A/D conversion of high accuracy is allowed.

    摘要翻译： 在流水线型A / D转换器中，第一级的A / D转换器模块的采样/保持减法器电路对模拟电压进行采样，并在第一阶段输出偏移电压，并且减去A / D转换器从第二阶段的采样模拟电压。 后级的A / D转换器模块的A / D转换器从第二相的采样保持电路的输出电压中减去第一相的采样/保持电路的输出电压，并将其转换 减去结果成数字代码。 除去包含在采样/保持抑制电路中的差分放大器的偏移的影响，使得允许高精度的A / D转换。

    Comparator bank of A/D converter
    48.
    发明授权
    Comparator bank of A/D converter 失效
    比较器A / D转换器组

    公开(公告)号：US4827262A

    公开(公告)日：1989-05-02

    申请号：US76858

    申请日：1987-07-23

    申请人： Toshio Kumamoto ,  Masao Nakaya

    发明人： Toshio Kumamoto ,  Masao Nakaya

    IPC分类号： H03M1/36 ,  H03M1/00 ,  H03M1/78

    CPC分类号： H03M1/361

    摘要： A comparator bank of an A/D converter comprising a plurality of comparators arranged into rows in a folded-back shape and a supply voltage line and a ground line in parallel with each other and connected to the comparators to provide reference potentials thereto according to a distribution shape which rises and falls continuously along the rows of the comparators whereby the linearity of the A/D converter is effectively maintained. The nodes of the comparators do not intersect and are arranged to successively become further from reference points set at the terminals of the supply voltage and ground lines.

    摘要翻译： 一种A / D转换器的比较器组，包括多个比较器，其布置成折叠形状的行，并且电源电压线和地线彼此并联连接并连接到比较器，以根据 分布形状沿着比较器的行连续地上升和下降，从而有效地保持A / D转换器的线性。 比较器的节点不相交并且被布置成从设置在电源电压和接地线的端子处的参考点依次变得更远。

    Semiconductor device
    49.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08237282B2

    公开(公告)日：2012-08-07

    申请号：US13030861

    申请日：2011-02-18

    申请人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

    发明人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

    IPC分类号： H01L23/522

    CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

    摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

    ΔΣ-type A/D converter
    50.
    发明授权
    ΔΣ-type A/D converter 有权
    ＆Dgr＆amp; S型A / D转换器

    公开(公告)号：US07952506B2

    公开(公告)日：2011-05-31

    申请号：US12911286

    申请日：2010-10-25

    申请人： Toshio Kumamoto ,  Takashi Okuda ,  Tatsuo Sengoku ,  Akira Kitaguchi

    发明人： Toshio Kumamoto ,  Takashi Okuda ,  Tatsuo Sengoku ,  Akira Kitaguchi

    IPC分类号： H03M3/00

    CPC分类号： H03M3/328 ,  H03M3/33 ,  H03M3/43 ,  H03M3/452

    摘要： There is provided a technique for reducing the adverse effect of idle tones in the channels in a ΔΣ-type A/D converter including a plurality of channels for converting analog input signals into digital signals. The ΔΣ-type A/D converter includes an L channel for converting a left analog input signal into a digital signal and an R channel for converting a right analog input signal into a digital signal. Each of the L channel and the R channel includes a DC dither circuit for generating a DC addition voltage for shifting the frequency of an idle tone. In the L channel and the R channel, DC addition voltages generated by DC dither circuits are different from each other.

    摘要翻译： 提供了一种用于减少包括用于将模拟输入信号转换为数字信号的多个通道的＆Dgr＆amp; S型A / D转换器中的通道中的空闲音调的不利影响的技术。 ＆amp; S＆amp; S型A / D转换器包括用于将左模拟输入信号转换为数字信号的L通道和用于将右模拟输入信号转换为数字信号的R通道。 L沟道和R沟道中的每一个包括用于产生用于移动空闲频率的频率的DC附加电压的DC抖动电路。 在L沟道和R沟道中，由DC抖动电路产生的直流相加电压彼此不同。