公开(公告)号：US06946865B2

公开(公告)日：2005-09-20

申请号：US10619601

申请日：2003-07-16

申请人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Susumu Narita

发明人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Susumu Narita

IPC分类号： G11C5/14 ,  H03K19/00 ,  G01R31/28

CPC分类号： H03K19/0016

摘要： A semiconductor integrated circuit apparatus includes a first controlled circuit halving at least one MOS transistor and a substrate bias control unit for generating a substrate bias voltage of the MOS transistor, wherein when the substrate bias control unit is set in a first mode, a comparatively large current is allowed to flow between the source and drain of the MOS transistor, while when the substrate bias control unit is set in a second mode, the comparatively large current allowed to flow between the source and drain of the MOS transistor is controlled to a current of smaller value. The value of the substrate bias applied to the first controlled circuit is larger in the second mode than in the first mode for the substrate bias of the PMOS transistor, and smaller in the second mode than in the first mode for the substrate bias of the NMOS transistor. The power supply voltage applied to the first controlled circuit is controlled to a smaller value in the second mode than in the first mode.

摘要翻译： 一种半导体集成电路装置，包括：至少一个MOS晶体管的第一受控电路和用于产生MOS晶体管的衬底偏置电压的衬底偏置控制单元，其中当衬底偏置控制单元设置在第一模式时，相对较大 允许电流在MOS晶体管的源极和漏极之间流动，而当衬底偏置控制单元设置为第二模式时，允许在MOS晶体管的源极和漏极之间流动的较大电流被控制为电流 价值较小。 施加到第一受控电路的衬底偏置的值在PMOS晶体管的衬底偏压的第二模式中比在第一模式中大，而在第二模式中比在用于NMOS的衬底偏置的第一模式更小 晶体管。 施加到第一受控电路的电源电压在第二模式中被控制为比在第一模式中更小的值。

公开(公告)号：US06715090B1

公开(公告)日：2004-03-30

申请号：US09308488

申请日：1999-05-20

申请人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

发明人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

IPC分类号： G06F130

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US06683503B2

公开(公告)日：2004-01-27

申请号：US09141343

申请日：1998-08-27

申请人： Hiroyuki Mizuno ,  Hirokazu Aoki ,  Koichiro Ishibashi

发明人： Hiroyuki Mizuno ,  Hirokazu Aoki ,  Koichiro Ishibashi

IPC分类号： H03B2700

CPC分类号： H03L7/0805 ,  G06F1/10 ,  H03K3/0231 ,  H03K3/03 ,  H03K3/0322 ,  H03L7/00 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/18

摘要： An oscillation circuit provides clock signals and a clock distribution circuit or system of circuits having low skew and low jitter to logic circuits and memory circuits of a microprocessor or the like. Further, a semiconductor integrated circuit device of high speed is provided as a result of the stable clock signal that is generated and distributed. The oscillation circuit is in a semiconductor integrated circuit device having a plurality of oscillators each having an oscillation node, wherein the oscillation nodes of each of the oscillators are connected together by a conductive wiring line that may be a closed loop. The oscillators are synchronized to oscillate at substantially the same frequency. The oscillators are connected to the conductive wiring line at connecting points having substantially the same interval of conductive wiring lengths between the connection points, which leads to synchronizing the oscillators to oscillate with a substantially identical phase. The conductive wiring line can also be formed in the shape of a mesh with the interval of length of the conductive wiring line between the connection points being at least 50 &mgr;m. The oscillators are ring oscillation circuits having inverters connected in a ring shape wherein an output of at least one inverter of each ring oscillation circuit is connected to the conductive wiring. Alternatively, the oscillators may be delay lines having multistage connected inverters with at least one inverter connected to the conductive wiring line.

公开(公告)号：US06259284B1

公开(公告)日：2001-07-10

申请号：US09470256

申请日：1999-12-22

申请人： Changku Hwang ,  Hiroyuki Mizuno ,  Masayuki Miyazaki

发明人： Changku Hwang ,  Hiroyuki Mizuno ,  Masayuki Miyazaki

IPC分类号： H03L700

CPC分类号： H03K17/284 ,  H03K17/223

摘要： A novel structure and method are taught for fully discharging a capacitor and thereby reducing the capacitance needed to achieve a desired RC time constant. The invention overcomes the previously encountered problem of using a large and area-inefficient capacitor. The invention allows for conservation of integrated circuit space and is cost effective.

摘要翻译： 教导了一种新颖的结构和方法来完全放电电容器，从而减少实现期望的RC时间常数所需的电容。 本发明克服了先前遇到的使用大面积低效电容器的问题。 本发明允许对集成电路空间的保护，并且是成本有效的。

公开(公告)号：US09151630B2

公开(公告)日：2015-10-06

申请号：US13523193

申请日：2012-06-14

申请人： Naoki Miura ,  Junichi Nonomura ,  Junki Yamakawa ,  Hiroyuki Mizuno

发明人： Naoki Miura ,  Junichi Nonomura ,  Junki Yamakawa ,  Hiroyuki Mizuno

IPC分类号： G06F19/00 ,  G06G7/70 ,  G01C21/34

CPC分类号： G01C21/3469 ,  B60K2350/1092 ,  Y02T10/84

摘要： Evaluation indication systems, methods, and programs display a current position of a vehicle and a map around the current position on a display unit, acquire current evaluations that indicate evaluations of fuel consumption in current travel of the vehicle by unit sections, and acquire previous evaluations that indicate evaluations of fuel consumption of the vehicle in a past prior to the current travel by unit sections. The systems, methods, and programs indicate the current evaluations and the previous evaluations together by unit sections on the map.

摘要翻译： 评估指示系统，方法和程序在显示单元上显示车辆的当前位置和当前位置周围的地图，获取指示车辆按单元部分的当前行驶中的燃料消耗的评估的当前评估，并且获取先前的评估 这表示在单位部门当前旅行之前过去的车辆燃料消耗的评估。 系统，方法和程序通过地图上的单位部分一起显示当前的评估和以前的评估。

公开(公告)号：US08674745B2

公开(公告)日：2014-03-18

申请号：US13406715

申请日：2012-02-28

申请人： Kazuo Tanaka ,  Hiroyuki Mizuno ,  Rie Nishiyama ,  Manabu Miyamoto

发明人： Kazuo Tanaka ,  Hiroyuki Mizuno ,  Rie Nishiyama ,  Manabu Miyamoto

IPC分类号： H03L5/00

CPC分类号： H03K3/356113 ,  H01L2924/0002 ,  H03K3/356104 ,  H01L2924/00

摘要： In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

摘要翻译： 在安装在使用多个高压和低压电源的集成电路装置中的电平转换电路中，提供到差分输入的输入。 在降压电路中，栅极和漏极之间以及栅极和源极之间未提供3.3 V的MOS晶体管使用薄的氧化物层。 在升高电路中，提供逻辑运算功能。

公开(公告)号：US08320703B2

公开(公告)日：2012-11-27

申请号：US11945729

申请日：2007-11-27

申请人： Hiroyuki Mizuno

发明人： Hiroyuki Mizuno

IPC分类号： G06K9/40

CPC分类号： G06T5/006

摘要： An image processing method executes image processing to correct a non-uniform perceived resolution caused by image distortion correction, thereby achieving a uniform perceived resolution over an entire displayed image. The image processing method includes the step of adjusting an aperture compensation signal using distortion correcting data to correct a non-uniform perceived resolution caused in an image through partial conversion of magnification ratio by image distortion correction, thereby achieving a uniform perceived resolution.

摘要翻译： 图像处理方法执行图像处理以校正由图像失真校正引起的不均匀的感知分辨率，从而在整个显示图像上实现均匀的感知分辨率。 图像处理方法包括使用失真校正数据调整孔径补偿信号的步骤，以通过图像失真校正通过部分转换放大率来校正在图像中引起的不均匀的感觉分辨率，由此实现均匀的感知分辨率。

公开(公告)号：US08199549B2

公开(公告)日：2012-06-12

申请号：US12859445

申请日：2010-08-19

申请人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

发明人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

IPC分类号： G11C5/06

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

公开(公告)号：US08063691B2

公开(公告)日：2011-11-22

申请号：US13020169

申请日：2011-02-03

申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yoshihiko Yasu ,  Nobuhiro Oodaira

发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yoshihiko Yasu ,  Nobuhiro Oodaira

IPC分类号： H03L5/00

CPC分类号： H03K19/0016 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0928 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

摘要翻译： 具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。 第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。 转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。 转换电路（MIO1〜MIO4）通常用于连接电路块。

公开(公告)号：US20110025409A1

公开(公告)日：2011-02-03

申请号：US12923681

申请日：2010-10-04

申请人： Hiroyuki Mizuno

发明人： Hiroyuki Mizuno

IPC分类号： G05F1/10

CPC分类号： G06F1/324 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3296 ,  H03K19/0016 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20 ,  Y10T307/25 ,  Y10T307/406

摘要： A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

摘要翻译： 一种用于快速和低功率操作的半导体集成电路器件，包括芯片的多个电路块，每个电路块具有不同功耗值的多个状态。 功率管理电路通过考虑每个电路块的功耗和每个电路块中的每个状态转换来确定每个电路块的状态，以便不超过半导体集成电路器件的最大功耗值。 最大功耗值可以在制造后预设或调节。