公开(公告)号：US20220415555A1

公开(公告)日：2022-12-29

申请号：US17359165

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Qiang Yu ,  Adel Elsherbini ,  Kimin Jun

IPC: H01F27/06 ,  H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01F27/28 ,  H01L21/50

Abstract: Methods and apparatus for inductor and transformer semiconductor devices using hybrid bonding technology are disclosed. An example semiconductor device includes a first standoff substrate; a second standoff substrate adjacent the first standoff substrate; and a conductive layer adjacent at least one of the first standoff substrate or the second standoff substrate.

公开(公告)号：US11417586B2

公开(公告)日：2022-08-16

申请号：US16141746

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Johanna Swan

IPC: H01L23/473 ,  H01L23/498 ,  H01L21/48 ,  H01L23/427 ,  H01L25/065 ,  H01L23/00

Abstract: An integrated circuit structure may be formed having a substrate, at least one integrated circuit device embedded in and electrically attached to the substrate, and at least one heat transfer fluid conduit extending through the substrate, wherein the heat transfer fluid conduit is electrically attached to the at least one integrated circuit device. In one embodiment, the at least one heat transfer fluid conduit is a power transfer route for the at least one integrated circuit device.

公开(公告)号：US20210375830A1

公开(公告)日：2021-12-02

申请号：US17399185

申请日：2021-08-11

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Johanna Swan ,  Shawna Liff ,  Patrick Morrow ,  Gerald Pasdast ,  Van Le

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00

Abstract: Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

公开(公告)号：US11183477B2

公开(公告)日：2021-11-23

申请号：US16584522

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Nagatoshi Tsunoda ,  Jimin Yao

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.

公开(公告)号：US10998302B2

公开(公告)日：2021-05-04

申请号：US16586167

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Van Le ,  Johanna Swan ,  Shawna Liff ,  Patrick Morrow ,  Gerald Pasdast ,  Min Huang

IPC: H01L25/18 ,  G06F13/40 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L25/075 ,  H01L21/768 ,  H01L25/07 ,  H01L25/04

Abstract: Techniques and mechanisms for providing at a packaged device an integrated circuit (IC) chip and a chiplet, wherein memory resources of the chiplet are accessible by a processor core of the IC chip. In an embodiment, a hardware interface of the packaged device includes first conductive contacts at a side of the chiplet, wherein second conductive contacts of the hardware interface are electrically interconnected to the IC chip each via a respective path which is independent of the chiplet. In another embodiment, one or more of the first conductive contacts are configured to deliver power, or communicate a signal, to a device layer of one of the IC chip or the chiplet.

公开(公告)号：US20200013770A1

公开(公告)日：2020-01-09

申请号：US16030196

申请日：2018-07-09

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Krishna Bharath ,  Mathew Manusharow

IPC: H01L27/01 ,  H01L23/498 ,  H01L49/02

Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first substrate surface, one or more second conductive contacts on a second substrate surface opposite the first substrate surface, a core layer comprising glass between the first and the second substrate surfaces, and one or more thin film capacitors on the glass core conductively coupled with one of the first conductive contacts and one of the second conductive contacts, wherein the thin film capacitor comprises a first metal layer on a surface of the glass core, a thin film dielectric material on a surface of the first metal layer, and a second metal layer on a surface of the thin film dielectric material. Other embodiments are also disclosed and claimed.

公开(公告)号：US09820384B2

公开(公告)日：2017-11-14

申请号：US14102676

申请日：2013-12-11

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Robert L. Sankman ,  Charles Gealer ,  Omkar Karhade ,  John S. Guzek ,  Ravi V. Mahajan ,  James C. Matayabas, Jr. ,  Johanna Swan ,  Feras Eid ,  Shawna Liff ,  Timothy McIntosh ,  Telesphor Kamgaing ,  Adel Elsherbini ,  Kemal Aygun

IPC: H05K1/18 ,  H05K13/04 ,  H01L23/00 ,  H05K1/03 ,  G06F1/16 ,  H01L21/56

CPC classification number: H05K1/189 ,  G06F1/163 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H05K1/0393 ,  H05K1/181 ,  H05K1/185 ,  H05K13/0469 ,  H05K2201/0137 ,  H05K2203/1469 ,  Y10T29/49146 ,  H01L2924/00

Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.

公开(公告)号：US09773742B2

公开(公告)日：2017-09-26

申请号：US14132729

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Adel Elsherbini ,  Valluri Rao

IPC: H01Q21/06 ,  H01Q1/38 ,  H01L23/66 ,  H01Q21/00 ,  H01L21/48 ,  H01L23/498 ,  H01L21/52 ,  H01Q1/22 ,  H01Q23/00 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/52 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/20 ,  H01L2223/6622 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q21/0006 ,  H01Q21/0093 ,  H01Q23/00

Abstract: Embodiments of an embedded mm-wave radio integrated circuit into a substrate of a phased array module are disclosed. In some embodiments, the phased array module includes a first set of substrate layers made of a first material. The mm-wave radio integrated circuit may be embedded in the first set of substrate layers. A second set of substrate layers may be coupled to the first set of substrate layers. The second set of substrate layers may be made of a second material that has a lower electrical loss than the first material. The second set of substrate layers may include a plurality of antenna elements coupled through vias to the mm-wave radio integrated circuit.

公开(公告)号：US20170156202A1

公开(公告)日：2017-06-01

申请号：US14954632

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Adel Elsherbini ,  Robert L. Sankman ,  Kemal Aygun

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0216 ,  H01L23/552 ,  H05K1/025 ,  H05K1/181 ,  H05K3/284 ,  H05K2203/1322 ,  Y02P70/611

Abstract: An electronic package having a substrate that includes signal traces and ground traces; an electronic component mounted on an upper surface of the substrate such that the electronic component is electrically connected to the signal traces and the ground traces in the substrate; an insulating layer covering the electronic component and the upper surface of the substrate; and an electromagnetic interference shielding mold covering the insulation layer such that the electromagnetic interference shielding mold is electrically connected to the ground traces in the substrate. In some forms of the electronic package, the electromagnetic interference shielding mold is electrically connected to the ground traces through openings in the insulation layer.

公开(公告)号：US12288746B2

公开(公告)日：2025-04-29

申请号：US16727747

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Mauro Kobrinsky ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast ,  Sathya Narasimman Tiagaraj

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.