公开(公告)号：US10360176B2

公开(公告)日：2019-07-23

申请号：US13997996

申请日：2013-01-16

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Vadim Makhervaks ,  Ben-Zion Friedman ,  Phil Cayton ,  Theodore L. Willke

IPC: G06F3/06 ,  G06F13/42 ,  G06F21/44 ,  G06F21/79 ,  G06F21/80 ,  H04L29/06 ,  H04L29/08 ,  G06F15/167 ,  G06F15/173

Abstract: Examples are disclosed for command validation for access to a storage device maintained at a server. In some examples, a network input/output device coupled to the server may receive the command from a client remote to the server. For these examples, elements or modules of the network input/output device may be capable of validating the command and reporting the status of the received command to the client. Other examples are described and claimed.

公开(公告)号：US10346175B2

公开(公告)日：2019-07-09

申请号：US15425908

申请日：2017-02-06

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Ben-Zion Friedman

IPC: G06F9/38 ,  G06F1/32 ,  G06F9/46 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/50

Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

公开(公告)号：US20180322913A1

公开(公告)日：2018-11-08

申请号：US15589893

申请日：2017-05-08

Applicant: Intel Corporation

Inventor： Ben-Zion Friedman ,  Eliezer Tamir ,  Manasi Deval

IPC: G11C11/4076 ,  G06F13/16 ,  G11C8/18 ,  G06F12/06 ,  G06F13/42

CPC classification number: G11C11/4076 ,  G06F11/00 ,  G06F12/02 ,  G06F12/063 ,  G06F12/0653 ,  G06F13/1626 ,  G06F13/4217 ,  G11C8/00 ,  G11C8/18

Abstract: Disclosed is a mechanism maintain flow rate limits to flows in a server operating in a single root input/output virtualization (SR-IOV) environment. A transmit pipeline assigns a dedicated transmit queue to a flow. A scheduler allocates a flow transmit bandwidth to the dedicated transmit queue to enforce the flow rate limit. The transmit pipeline assigns the dedicated transmit queue to the flow upon receiving a packet of the flow. A queue identifier (ID) for the dedicated transmit queue is forwarded to a tenant process acting as a source of the flow to support forwarding of packets of the flow to the proper transmit queue. The transmit pipeline maintains security by comparing packet destinations of packets with the destination of the flow associated with the dedicated transmit queue. Packets in the dedicated destination queue with destinations that do not match the flow destination may be dropped.

公开(公告)号：US20180287941A1

公开(公告)日：2018-10-04

申请号：US15476638

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Eliel Louzoun ,  Ben-Zion Friedman ,  Eli Sorin ,  Nir Haber

IPC: H04L12/741 ,  H04L29/06

Abstract: Disclosed is a mechanism for maintaining a single lookup table entry for symmetric/bidirectional flows. Multiple recipes are stored for each flow. A recipe is employed to select address information from an incoming packet header based on the packet's direction. The address information and an index are employed to generate a lookup key to find the single lookup table entry with the pertinent switching information. The recipe further indicates action pointers in the lookup table entry that are specific to direction. The action pointers point to an address in an action table that contains instructions for actions that are applied to the packet during switching based on the packet's direction.

公开(公告)号：US20180181530A1

公开(公告)日：2018-06-28

申请号：US15392181

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Tomasz Kantecki ,  Ben-Zion Friedman ,  Niall D. McDonnell ,  Bruce Richardson

IPC: G06F13/42 ,  G06F12/0806 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F12/0875 ,  G06F13/126 ,  G06F13/4022 ,  G06F2212/452 ,  G06F2213/0026

Abstract: Examples include techniques for coalescing doorbells in a request message. Example techniques include gathering doorbells to access a device. The gathered are combined in a cache line structure and the cache line structure is written to a cache or buffer for a central processing unit in a single write operation.

公开(公告)号：US20180173675A1

公开(公告)日：2018-06-21

申请号：US15386919

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Ben-Zion Friedman

IPC: G06F15/80

CPC classification number: G06F15/80 ,  G06F8/47 ,  G06F9/44547

Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

公开(公告)号：US20180173529A1

公开(公告)日：2018-06-21

申请号：US15386990

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Ben-Zion Friedman

IPC: G06F9/30 ,  G06F9/48

CPC classification number: G06F9/485 ,  G06F8/41 ,  G06F9/3009 ,  G06F9/4856 ,  G06F9/5088 ,  Y02D10/24 ,  Y02D10/32

Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

公开(公告)号：US09973335B2

公开(公告)日：2018-05-15

申请号：US13839080

申请日：2013-03-15

Applicant: INTEL CORPORATION

Inventor： Ben-Zion Friedman ,  Eliezer Tamir ,  Eliel Louzoun ,  Ohad Falik

IPC: H04L9/06 ,  G06F21/72 ,  H04L29/06

CPC classification number: H04L9/0618 ,  G06F21/72 ,  H04L63/0485

Abstract: Examples are disclosed for exchanging a key between an input/output device for network device and a first processing element operating on the network device. Data having a destination associated with the first processing element may be received by the input/output device. The exchanged key may be used to encrypt the received data. The encrypted data may then be sent to a buffer maintained at least in part in a memory for the network device. The memory may be arranged to enable sharing of the buffer with at least a second processing element operating on the network device. Examples are also disclosed for the processing element to receive an indication of the storing of the encrypted data in the buffer. The processing element may then obtain the encrypted data from the buffer and decrypt the data using the exchanged key.

公开(公告)号：US09742616B2

公开(公告)日：2017-08-22

申请号：US14580766

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Nrupal Jani ,  Ilango Ganga ,  Daniel Daly ,  John Fastabend ,  Neerav Parikh ,  Elizabeth Kappler ,  Brian J. Skerry ,  Calin Gherghe ,  Sanjeev Jain ,  Ben-Zion Friedman

IPC: H04L29/06 ,  H04L12/54 ,  H04L12/931 ,  G06F9/455

CPC classification number: H04L29/0653 ,  G06F9/45558 ,  G06F2009/45595 ,  H04L12/56 ,  H04L49/70 ,  H04L69/22

Abstract: Devices and techniques for indicating packet processing hints are described herein. A device may receive a data packet. The device may extract a match-action attribute from the data packet that specifies an action to be applied to the data packet. The device may generate a hint field based on the match-action attribute. The hint field may include information to be used for handling the data packet. Other embodiments are also described.

公开(公告)号：US20170149926A1

公开(公告)日：2017-05-25

申请号：US15426718

申请日：2017-02-07

Applicant: Intel Corporation

Inventor： Ren Wang ,  Sameh Gobriel ,  Christian Maciocco ,  Tsung-Yuan C. Tai ,  Ben-Zion Friedman ,  Hang T. Nguyen ,  Namakkal N. Venkatesan ,  Michael A. O'Hanlon ,  Shrikant M. Shah ,  Sanjeev Jain

IPC: H04L29/08 ,  H04L12/743 ,  H04L12/721 ,  H04L12/24 ,  H04L12/741

CPC classification number: H04L67/2852 ,  H04L41/0893 ,  H04L45/38 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/00

Abstract: Technologies for identifying a cache line of a network packet for eviction from an on-processor cache of a network device communicatively coupled to a network controller. The network device is configured to determine whether a cache line of the cache corresponding to the network packet is to be evicted from the cache based on a determination that the network packet is not needed subsequent to processing the network packet, and provide an indication that the cache line is to be evicted from the cache based on an eviction policy received from the network controller.