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    Memory subsystem I/O performance based on in-system empirical testing
    41.
    发明授权
    Memory subsystem I/O performance based on in-system empirical testing 有权

    公开(公告)号：US10446222B2

    公开(公告)日：2019-10-15

    申请号：US15372031

    申请日：2016-12-07

    Applicant: Intel Corporation

    Inventor： Theodore Z. Schoenborn ,  Christopher P. Mozak

    IPC: G06F13/40 ,  G11C11/4093 ,  G11C29/56 ,  G11C29/06 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/04

    Abstract: A memory subsystem empirically tests performance parameters of I/O with a memory device. Based on the empirical testing, the memory subsystem can set the performance parameters specific to the system in which the memory subsystem is included. A test system performs the testing. For each of multiple different settings for multiple different I/O circuit parameters, the test system sets a value for each I/O circuit parameter, generates test traffic to stress test the memory device with the parameter value(s), and measures an operating margin for the I/O performance characteristic. The test system further executes a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold and performance of at least one of the I/O circuit parameters is increased. The memory subsystem sets runtime values for the I/O circuit parameters based on the search function.

    High-voltage power gating
    45.
    发明授权
    High-voltage power gating 有权
    高压电源门控

    公开(公告)号：US09350165B2

    公开(公告)日：2016-05-24

    申请号：US13669204

    申请日：2012-11-05

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  Hong Yun Tan

    IPC: H02H9/02 ,  H02H9/04 ,  H03K17/10 ,  H03K17/22

    CPC classification number: H02H9/046 ,  H03K17/102 ,  H03K17/223

    Abstract: Power gating circuits. A transistor stack is coupled between a voltage supply to provide a gated supply voltage. The supply voltage is greater than the maximum junction voltage of the individual transistors in the transistor stack. Termination circuitry for input/output (I/O) lines coupled to operate using the gated supply voltage. The termination circuitry comprising at least a resistive element coupled between an I/O interface and a termination voltage supply.

    Abstract translation: 电源门控电路。 晶体管堆叠耦合在电压源之间以提供门控电源电压。 电源电压大于晶体管堆叠中单个晶体管的最大结电压。 用于输入/输出（I / O）线的端接电路，其耦合以使用门控电源电压进行操作。 所述终端电路至少包括耦合在I / O接口和终端电压源之间的电阻元件。

    Memory subsystem data bus stress testing
    46.
    发明授权
    Memory subsystem data bus stress testing 有权
    内存子系统数据总线压力测试

    公开(公告)号：US09009531B2

    公开(公告)日：2015-04-14

    申请号：US13706177

    申请日：2012-12-05

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  Theodore Z. Schoenborn ,  James M. Shehadi ,  David G. Ellis

    IPC: G06F11/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/36 ,  G11C29/50 ,  G11C29/52

    CPC classification number: G11C29/02 ,  G11C29/022 ,  G11C29/06 ,  G11C29/36 ,  G11C29/50012 ,  G11C29/52

    Abstract: A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a test transaction. The test transaction indicates one or more I/O operations to perform on an associated memory device. The test signal generator can generate data signals from various different pattern generators. The memory controller scheduler schedules the test data signal pattern, and sends it to the memory device. The memory device can then execute I/O operation(s) to implement the test transaction. The memory controller can read back data written to a specific address of the memory device and compare the read back data with expected data. When the read back data and the expected data do not match, the memory controller can record an error. The error can include the specific address of the error, the specific data, and/or encoded data.

    Abstract translation: 存储器子系统包括存储器控制器的测试信号发生器，其响应于存储器控制器接收测试事务而产生测试数据信号。 测试事务指示在相关联的存储设备上执行的一个或多个I / O操作。 测试信号发生器可以从各种不同的模式发生器产生数据信号。 存储器控制器调度器调度测试数据信号模式，并将其发送到存储器件。 然后，存储器件可以执行I / O操作来实现测试事务。 存储器控制器可以读取写入存储器件的特定地址的数据，并将回读数据与预期数据进行比较。 当回读数据和预期数据不匹配时，存储器控制器可以记录错误。 该错误可以包括错误的具体地址，特定数据和/或编码数据。

    Functional memory array testing with a transaction-level test engine
    47.
    发明授权
    Functional memory array testing with a transaction-level test engine 有权
    功能性内存阵列测试与事务级测试引擎

    公开(公告)号：US09003246B2

    公开(公告)日：2015-04-07

    申请号：US13631962

    申请日：2012-09-29

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  Theodore Z. Schoenborn ,  James M. Shehadi

    IPC: G11C29/00 ,  G11C29/08 ,  G11C29/56

    CPC classification number: G11C29/08 ,  G11C29/56 ,  G11C2029/5602

    Abstract: A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine hardware is configurable for different tests. The test engine identifies a range of addresses through which to iterate a test sequence in response to receiving a software instruction indicating a test to perform. For each iteration of the test, the test engine, via the selected hardware, generates a memory access transaction, selects an address from the range, and sends the transaction to the memory controller. The memory controller schedules memory device commands in response to the transaction, which causes the memory device to execute operations to carry out the transaction.

    Abstract translation: 存储器子系统包括耦合到存储器控制器的测试引擎，其可以绕过存储器地址解码器来向存储器控制器提供存储器访问事务。 测试引擎硬件可配置为不同的测试。 测试引擎识别响应于接收到指示要执行的测试的软件指令来迭代测试序列的地址范围。 对于测试的每次迭代，测试引擎通过选定的硬件生成内存访问事务，从范围中选择一个地址，并将事务发送到内存控制器。 存储器控制器响应于事务来调度存储器设备命令，这导致存储器件执行操作来执行事务。

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