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    Use of error correction pointers to handle errors in memory
    41.
    发明授权
    Use of error correction pointers to handle errors in memory 有权
    使用纠错指针来处理内存中的错误

    公开(公告)号：US09250990B2

    公开(公告)日：2016-02-02

    申请号：US14129070

    申请日：2013-09-24

    Applicant: INTEL CORPORATION

    Inventor： Ravi H. Motwani ,  Kiran Pangal

    IPC: G06F11/07 ,  G06F11/10

    CPC classification number: G06F11/073 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/1048

    Abstract: Methods, apparatuses, and systems related to use of error correction pointers (ECPs) to handle hard errors in memory are described herein. In embodiments, a read module of a memory controller may read a codeword stored in a memory. The read module may determine a number of hard errors in the codeword. Responsive to a determination that the number of hard errors exceeds a threshold, the read module may store ECP information associated with the hard errors. The read module may include an error correction code (ECC) module to perform an ECC process on the codeword. The read module may use the ECP information to decode the codeword to recover the data responsive to a determination that the ECC process failed. Other embodiments may be described and claimed.

    Abstract translation: 这里描述了使用纠错指针（ECP）来处理存储器中的硬错误的方法，装置和系统。 在实施例中，存储器控制器的读取模块可以读取存储在存储器中的代码字。 读取模块可以确定码字中的许多硬错误。 响应于确定硬错误的数量超过阈值，读取模块可以存储与硬错误相关联的ECP信息。 读取模块可以包括用于对码字执行ECC处理的纠错码（ECC）模块。 读取模块可以使用ECP信息来解码码字以响应于ECC过程失败的确定来恢复数据。 可以描述和要求保护其他实施例。

    Thermal-disturb mitigation in dual-deck cross-point memories
    43.
    发明授权
    Thermal-disturb mitigation in dual-deck cross-point memories 有权
    双层交叉点存储器中的热干扰减轻

    公开(公告)号：US09231202B2

    公开(公告)日：2016-01-05

    申请号：US13921672

    申请日：2013-06-19

    Applicant: Intel Corporation

    Inventor： Kiran Pangal ,  Max F. Hineman

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1293 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

    Abstract: A thermal isolation layer is formed between the bit line (BL) layers or word line (WL) layers of the decks of a multi-deck phase-change cross-point memory to mitigate thermal problem disturb of memory cells that tends to increase as memory sizes are scaled smaller. Embodiments of the subject matter disclosed herein are suitable for, but are not limited to, solid-state memory arrays and solid-state drives.

    Abstract translation: 在多层相变交叉点存储器的甲板的位线（BL）层或字线（WL）层之间形成热隔离层，以减轻趋向于作为存储器增加的存储器单元的热问题干扰 尺寸缩小。 本文公开的主题的实施例适用于但不限于固态存储器阵列和固态驱动器。

    Techniques for adaptive moving read references for memory cell read error recovery
    44.
    发明授权
    Techniques for adaptive moving read references for memory cell read error recovery 有权
    用于存储单元读取错误恢复的自适应移动读取参考的技术

    公开(公告)号：US09208022B2

    公开(公告)日：2015-12-08

    申请号：US14499003

    申请日：2014-09-26

    Applicant: Intel Corporation

    Inventor： Lark-Hoon Leem ,  Kiran Pangal ,  Xin Guo

    IPC: G06F11/10 ,  G06F11/07 ,  G06F11/00 ,  G11C29/00 ,  G11C11/56 ,  G11C16/34

    CPC classification number: G06F11/1048 ,  G06F11/076 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3495 ,  G11C29/789

    Abstract: Examples are given for generating or providing a moving read reference (MRR) table for recovering from a read error of non-volatile memory included in a storage device. In some examples, priorities may be adaptively assigned to entries included in the MRR table. The entries may be ordered for use based on the assigned priorities. In other examples, the MRR table may be ordered for use such that entries with a single MRR value for each read reference value may be used first over entries having multiple MRR values for each read reference value. For these other examples, the MRR table may be adaptively reordered based on which entries were successful or unsuccessful in recovering from a read error but may still be arranged to have single MRR value entries used first for use to recover from another read error.

    Abstract translation: 给出了用于生成或提供用于从包括在存储设备中的非易失性存储器的读取错误中恢复的移动读取参考（MRR）表的示例。 在一些示例中，可以将优先级自适应地分配给包括在MRR表中的条目。 可以根据分配的优先级订购条目。 在其他示例中，MRR表可以被排序使用，使得对于每个读取参考值具有单个MRR值的条目可以首先用于对于每个读取参考值具有多个MRR值的条目。 对于这些其他示例，可以基于哪些条目在从读取错误中恢复成功或不成功而自适应地重新排序MRR表，但是仍然可以被布置为具有首先使用的单个MRR值条目用于从另一读取错误中恢复。

    ERROR CORRECTION IN MEMORY
    46.
    发明申请
    ERROR CORRECTION IN MEMORY 审中-公开
    内存错误修正

    公开(公告)号：US20150149857A1

    公开(公告)日：2015-05-28

    申请号：US14091757

    申请日：2013-11-27

    Applicant: Intel Corporation

    Inventor： Ravi H. Motwani ,  Kiran Pangal

    IPC: H03M13/05 ,  G06F11/10

    CPC classification number: G06F11/1008 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1048 ,  H03M13/05 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/23 ,  H03M13/2957

    Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device for data stored in a memory, retrieve the data and an associated error correction codeword, send the data to a host device, apply an error correction routine to decode the error correction codeword retrieved with the data, and in response to an error in the error correction codeword, send a location of data associated with the error to the host device. Other embodiments are also disclosed and claimed.

    Abstract translation: 描述了存储器中用于纠错的装置，系统和方法。 在一个实施例中，控制器包括从主机设备接收存储在存储器中的数据的读取请求的逻辑，检索数据和相关联的纠错码字，将数据发送到主机设备，应用纠错例程来解码 使用数据检索的纠错码字，并且响应于纠错码字中的错误，向主机设备发送与该错误相关联的数据的位置。 还公开并要求保护其他实施例。

    Current delivery and spike mitigation in a memory cell array
    48.
    发明授权
    Current delivery and spike mitigation in a memory cell array 有权

    公开(公告)号：US11322546B2

    公开(公告)日：2022-05-03

    申请号：US16145084

    申请日：2018-09-27

    Applicant: Intel Corporation

    Inventor： Shafqat Ahmed ,  Kiran Pangal

    IPC: H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L27/11507 ,  H01L43/12 ,  H01L43/02 ,  G11C13/00 ,  H01L49/02

    Abstract: A single memory cell array is formed to maintain current delivery and mitigate current spike through the deposition of resistive materials in two or more regions of the array, including at least one region of memory cells nearer to contacts on the conductive lines and at least one region of memory cells farther from the contacts, where the contacts connect the conductive lines to the current source. Higher and lower resistive materials are introduced during the formation of the memory cells and the conductive lines based on the boundaries and dimensions of the two or more regions using a photo mask. Multiple memory cell arrays formed to maintain current delivery and mitigate current spike can be arranged into a three-dimensional memory cell array. The regions of memory cells in each memory cell array can vary depending on resistance at the contacts on the conductive lines that provide access to the memory cells, where the resistance can vary from one memory cell array to another.

    Multi-level cell (MLC) techniques and circuits for cross-point memory
    50.
    发明授权
    Multi-level cell (MLC) techniques and circuits for cross-point memory 有权

    公开(公告)号：US10957387B1

    公开(公告)日：2021-03-23

    申请号：US16687468

    申请日：2019-11-18

    Applicant: Intel Corporation

    Inventor： Davide Mantegazza ,  Kiran Pangal ,  Sanjay Rangan

    IPC: G11C11/00 ,  G11C11/56 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

    Abstract: Techniques for accessing multi-level cell (MLC) crosspoint memory cells are described. In one example, a circuit includes a crosspoint memory cell that can be in one of multiple resistive states (e.g., four or more resistive states). In one example, to perform a read, circuitry coupled with the memory cell applies one or more sub-reads at different read voltages. For example, the circuitry applies a first read voltage and detects if the memory cell thresholds in response to the first read voltage. If the memory cell thresholded in response to the first read voltage, the state of the memory cell can be determined without further reads. If the memory cell did not threshold in response to the first read voltage, a second read voltage with a greater magnitude is applied across the memory cell. If the memory cell thresholded in response to the second read voltage, the state of the memory cell can be determined without further reads. If the memory cell did not threshold in response to the first read voltage, a third read voltage with a greater magnitude is applied across the memory cell. In one example, the thresholding of the memory cell triggers the application of a write current to write back the state of the bit due to read disturb from the read.

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