公开(公告)号：US10930791B2

公开(公告)日：2021-02-23

申请号：US16325164

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Van H. Le ,  Rafael Rios ,  Shriram Shivaraman ,  Jack T. Kavalieros ,  Marko Radosavljevic

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/221 ,  H01L29/66

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors. For instance, there is disclosed in accordance with one embodiment a semiconductor device having therein a substrate; a bi-layer oxides layer formed from a first oxide material and a second oxide material, the first oxide material comprising a semiconducting oxide material and having different material properties from the second oxide material comprising a high mobility oxide material; a channel layer formed atop the substrate, the channel layer formed from the semiconducting oxide material of the bi-layer oxides layer; a high mobility oxide layer formed atop the channel layer, the high conductivity oxide layer formed from the high mobility oxide material of the bi-layer oxides layer; metallic contacts formed atop the high mobility oxide layer; a gate and a gate oxide material formed atop the high mobility oxide layer, the gate oxide material being in direct contact with the high mobility oxide layer; and spacers separating the metallic contacts from the gate and gate oxide material. Other related embodiments are disclosed.

公开(公告)号：US10825752B2

公开(公告)日：2020-11-03

申请号：US14775487

申请日：2013-06-18

Applicant: Intel Corporation

Inventor： Lei Jiang ,  Edwin B. Ramayya ,  Daniel Pantuso ,  Rafael Rios ,  Kelin J. Kuhn ,  Seiyon Kim

IPC: H01L23/38 ,  H01L21/8238 ,  H01L27/092 ,  H05K1/18

Abstract: Embodiments of the present disclosure describe techniques and configurations for integrated thermoelectric cooling. In one embodiment, a cooling assembly includes a semiconductor substrate, first circuitry disposed on the semiconductor substrate and configured to generate heat when in operation and second circuitry disposed on the semiconductor substrate and configured to remove the heat by thermoelectric cooling. Other embodiments may be described and/or claimed.

公开(公告)号：US10403733B2

公开(公告)日：2019-09-03

申请号：US15776752

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Van H. Le ,  Matthew V. Metz ,  Willy Rachmady ,  Jack T. Kavalieros ,  Rafael Rios

IPC: H01L29/76 ,  H01L29/51 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66

Abstract: Embodiments of the present disclosure describe semiconductor devices comprised of a semiconductor substrate with a metal oxide semiconductor field effect transistor having a channel including germanium or silicon-germanium, where a dielectric layer is coupled to the channel. The dielectric layer may include a metal oxide and at least one additional element, where the at least one additional element may increase a band gap of the dielectric layer. A gate electrode may be coupled to the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US09859368B2

公开(公告)日：2018-01-02

申请号：US15333123

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Mark Armstrong ,  Rafael Rios ,  Abhijit Jayant Pethe ,  Willy Rachmady

IPC: H01L29/06 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/3115 ,  H01L29/78 ,  H01L29/786 ,  H01L29/08 ,  H01L29/66 ,  B82Y40/00

CPC classification number: H01L29/0673 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/78696

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

公开(公告)号：US20170133493A1

公开(公告)日：2017-05-11

申请号：US15410548

申请日：2017-01-19

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, JR. ,  Ian A. Young ,  Kelin J. Kuhn

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/161 ,  H01L29/10 ,  H01L29/786 ,  H01L29/165

CPC classification number: H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

公开(公告)号：US20170018304A1

公开(公告)日：2017-01-19

申请号：US15282484

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Rafael Rios ,  Ian A. Young

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/145 ,  G11C11/412 ,  H01L27/1104 ,  H03K3/356104

Abstract: Embodiments include apparatuses, methods, and systems for a circuit to shift a voltage level. The circuit may include a first inverter that includes a first transistor coupled to pass a low voltage signal and a second inverter coupled to receive the low voltage signal. The circuit may further include a second transistor coupled to receive the low voltage signal from the second inverter to serve as a feedback device and produce a high voltage signal. In embodiments, the first transistor conducts asymmetrically to prevent crossover of the high voltage signal into the low voltage domain. A low voltage memory array is also described. In embodiments, the circuit to shift a voltage level may assist communication between a logic component including the low voltage memory array of a low voltage domain and a logic component of a high voltage domain. Additional embodiments may also be described.

Abstract translation: 实施例包括用于移位电压电平的电路的装置，方法和系统。 电路可以包括第一反相器，其包括耦合以传递低电压信号的第一晶体管和耦合以接收低电压信号的第二反相器。 电路还可以包括第二晶体管，其被耦合以从第二反相器接收低电压信号，以用作反馈装置并产生高电压信号。 在实施例中，第一晶体管不对称地导通，以防止高电压信号到低电压域的交叉。 还描述了低电压存储器阵列。 在实施例中，用于移位电压电平的电路可以有助于包括低电压域的低电压存储器阵列的逻辑部件与高电压域的逻辑部件之间的通信。 还可以描述另外的实施例。

公开(公告)号：US08853741B2

公开(公告)日：2014-10-07

申请号：US13964696

申请日：2013-08-12

Applicant: Intel Corporation

Inventor： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Titash Rakshit ,  Sivakumar Mudanai

IPC: H01L29/205 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/0669 ,  H01L29/205 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7857

Abstract: A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.

Abstract translation: 通过在JAM半导体主体的突出特征之下的反向偏压带将无连接累积模式（JAM）半导体器件从半导体衬底隔离。 制造JAM器件的过程包括植入和外延。