公开(公告)号：US09819362B2

公开(公告)日：2017-11-14

申请号：US14671140

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Pranav Kalavade

IPC: H03M13/15 ,  H03M13/11 ,  G06F11/10 ,  G11C29/02 ,  G11C29/42 ,  G11C29/52 ,  G11C7/10 ,  G11C16/04 ,  G11C29/12

CPC classification number: H03M13/1515 ,  G06F11/1012 ,  G06F11/1024 ,  G06F11/1068 ,  G11C7/1006 ,  G11C16/0483 ,  G11C29/025 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/1204 ,  H03M13/1102

Abstract: Described is a method which comprises performing a first read from a portion of a non-volatile memory, the first read to provide a first codeword; decoding the first codeword; determining whether the decoding operation failed; performing a second read from the portion of the non-volatile memory when it is determined that the decoding operation failed, the second read to provide a second codeword; and decoding the second codeword with an errors-and-erasures decoding process.

公开(公告)号：US09652321B2

公开(公告)日：2017-05-16

申请号：US14493956

申请日：2014-09-23

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Kiran Pangal

IPC: G06F11/10 ,  G11C29/52 ,  G06F12/02 ,  H03M13/11 ,  G11C29/04

CPC classification number: G06F11/1008 ,  G06F11/10 ,  G06F11/1068 ,  G06F11/108 ,  G06F12/0246 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1108

Abstract: Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device to read a line of data to the memory device, wherein the data is spread across a plurality (N) of dies and comprises an error correction code (ECC) spread across the plurality (N) of dies, retrieve the line of data from the memory device, perform an error correction code (ECC) check on the line of data retrieved from the memory device, and invoke a recovery algorithm in response to an error in the ECC check on the line of data retrieved from the memory device. Other embodiments are also disclosed and claimed.

公开(公告)号：US09619324B2

公开(公告)日：2017-04-11

申请号：US14126310

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Zion S. Kwok ,  Ravi H. Motwani ,  Kiran Pangal ,  Prashant S. Damle

IPC: G06F11/10 ,  G06F12/00 ,  G11C29/52 ,  H03M13/15

CPC classification number: G06F11/1068 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/108 ,  G06F12/00 ,  G06F2212/7207 ,  G11C29/52 ,  H03M13/1515 ,  H03M13/152

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to receive a read request for data stored in a memory, retrieve the data and at least one associated error correction codeword, wherein the data and an associated error correction codeword is distributed across a plurality of memory devices in memory, apply a first error correction routine to decode the error correction codeword retrieved with the data and in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of devices in memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US09535777B2

公开(公告)日：2017-01-03

申请号：US14087282

申请日：2013-11-22

Applicant: Intel Corporation

Inventor： Pranav Kalavade ,  Feng Zhu ,  Shyam Sunder Raghunathan ,  Ravi H. Motwani

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/07 ,  G11B20/18

CPC classification number: G06F11/0751 ,  G06F11/073 ,  G06F11/1012 ,  G11B20/1816

Abstract: Systems and methods of managing defects in nonvolatile storage systems that can be used to avoid an inadvertent loss of data, while maintaining as much useful memory in the nonvolatile storage systems as possible. The disclosed systems and methods can monitor a plurality of trigger events for detecting possible defects in one or more nonvolatile memory (NVM) devices included in the nonvolatile storage systems, and apply one or more defect management policies to the respective NVM devices based on the types of trigger events that resulted in detection of the possible defects. Such defect management policies can be used proactively to retire memory in the nonvolatile storage systems with increased granularity, focusing the retirement of memory on regions of nonvolatile memory that are likely to contain a defect.

Abstract translation: 管理非易失性存储系统中的缺陷的系统和方法，可用于避免无意中丢失数据，同时尽可能保持非易失性存储系统中有用的内存。 所公开的系统和方法可以监视多个触发事件，用于检测非易失性存储系统中包括的一个或多个非易失性存储器（NVM）设备中的可能缺陷，并且基于类型向相应的NVM设备应用一个或多个缺陷管理策略 的触发事件导致检测到可能的缺陷。 可以主动地使用这种缺陷管理策略来以更小的粒度来在非易失性存储系统中退出内存，将存储器的退出重点集中在可能包含缺陷的非易失性存储器的区域上。

公开(公告)号：US09438287B2

公开(公告)日：2016-09-06

申请号：US14562499

申请日：2014-12-05

Applicant: INTEL CORPORATION

Inventor： Ravi H. Motwani

IPC: H04B1/10 ,  H04B1/04 ,  H04L25/08

CPC classification number: H04B1/1036 ,  H04B1/0475 ,  H04B1/10 ,  H04B2001/1063 ,  H04L25/085

Abstract: Described is an apparatus comprising: a first sampler to oversample a signal, the signal being processed for transmission through a channel having a notch region; a bandpass filter with passband response to filter the oversampled signal in the notch region; and a first modulator to translate the filtered signal to a higher frequency band than a frequency band of the notch region. Described is a method performed by a transmitter, the method comprising: oversampling a signal; and translating, in response to the oversampling, signal content in a notch region of a channel to a frequency band which is higher than a frequency band of the notch region.

Abstract translation: 描述了一种装置，包括：第一采样器，用于对信号进行过采样，所述信号被处理以通过具有切口区域的通道传输; 具有通带响应的带通滤波器，以对陷波区域中的过采样信号进行滤波; 以及第一调制器，用于将经滤波的信号转换到比缺口区的频带更高的频带。 描述了由发射机执行的方法，该方法包括：对信号进行过采样; 并且响应于所述过采样将信道的陷波区域中的信号内容转换到高于所述切口区域的频带的频带。

公开(公告)号：US09317364B2

公开(公告)日：2016-04-19

申请号：US14129066

申请日：2013-09-25

Applicant: INTEL CORPORATION

Inventor： Ravi H. Motwani ,  Kiran Pangal

IPC: G11C29/00 ,  G06F11/10 ,  G06F13/16

CPC classification number: G06F11/1076 ,  G06F11/1012 ,  G06F13/16 ,  G06F13/1694 ,  G11C7/1006 ,  G11C13/0004 ,  G11C13/0069

Abstract: Methods, apparatuses, and systems are described related to memory controllers for memory. In one embodiment, a memory controller may include a distribution transformer configured to receive data to be stored into a memory, wherein the data has a distribution of m1:n1 ratio for bits having a first logic value and bits having a second logic value, where m1 and n1 are real numbers. The distribution transformer may transform the data into skewed data, wherein the skewed data has a distribution of m2:n2 ratio for bits having the first logic value and bits having the second logic value, where m2 and n2 are real numbers that are different from one another and respectively differ from m1 and n1. The distribution transformer may output the skewed data for storage in the memory. Other embodiments may be described and claimed.

Abstract translation: 描述与存储器的存储器控​​制器相关的方法，装置和系统。 在一个实施例中，存储器控制器可以包括被配置为接收要存储到存储器中的数据的分配变压器，其中所述数据具有用于具有第一逻辑值的位和具有第二逻辑值的位的m1：n1比率分布，其中 m1和n1是实数。 分配变压器可以将数据变换成偏斜数据，其中偏斜数据具有具有第一逻辑值的比特的m2：n2比率和具有第二逻辑值的比特的分布，其中m2和n2是不同于一个的实数 另一个，分别不同于m1和n1。 配电变压器可以输出偏斜数据以存储在存储器中。 可以描述和要求保护其他实施例。

公开(公告)号：US09037943B2

公开(公告)日：2015-05-19

申请号：US13662160

申请日：2012-10-26

Applicant: INTEL CORPORATION

Inventor： Ravi H. Motwani ,  Kiran Pangal

IPC: H03M13/00 ,  H03M13/29 ,  H03M13/09 ,  H03M13/11

CPC classification number: H03M13/2927 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/293 ,  H03M13/2948 ,  H03M13/2957

Abstract: Embodiments of apparatus, methods, storage drives, computer-readable media, systems and devices are described herein for identification of die of non-volatile memory for use in remedial action. In various embodiments, a first block may be configured to encode data to be stored in a non-volatile memory as a codeword. In various embodiments, the first block may be configured to store respective portions of the codeword in a distributed manner across a plurality of die of the non-volatile memory. In various embodiments, the first block may be configured to generate respective error detection codes for the plurality of die.

Abstract translation: 本文描述了装置，方法，存储驱动器，计算机可读介质，系统和设备的实施例，用于识别用于补救动作的非易失性存储器的管芯。 在各种实施例中，第一块可以被配置为将要存储在非易失性存储器中的数据编码为码字。 在各种实施例中，第一块可以被配置为以分布式方式存储码字的相应部分跨越非易失性存储器的多个管芯。 在各种实施例中，第一块可以被配置为为多个管芯生成相应的检错代码。

公开(公告)号：US08959407B2

公开(公告)日：2015-02-17

申请号：US13687951

申请日：2012-11-28

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Kiran Pangal

IPC: G06F11/00 ,  H03M13/13 ,  H03M13/37 ,  H03M13/00 ,  G06F11/10 ,  H03M13/11 ,  H03M13/29

CPC classification number: H03M13/13 ,  G06F11/1012 ,  H03M13/1102 ,  H03M13/29 ,  H03M13/2957 ,  H03M13/3723 ,  H03M13/3746 ,  H03M13/612 ,  H03M13/6337

Abstract: Embodiments include methods, apparatuses, and instructions for encoding a codeword of data as codeword portions stored across multiple die in a non-volatile memory. Embodiments further include a decoder which may be configured to decode the portions of the codeword using hard decision reads. The decoder may then be configured to estimate the quality of each die, and apply a scaling factor to the decoded codeword portions such that confidence or reliability information can be determined for the codeword.

Abstract translation: 实施例包括用于将数据的码字编码为在非易失性存储器中跨多个存储器存储的码字部分的方法，装置和指令。 实施例还包括解码器，其可以被配置为使用硬判决读取对码字的部分进行解码。 解码器然后可以被配置为估计每个管芯的质量，并将缩放因子应用于解码的码字部分，使得可以为码字确定置信度或可靠性信息。

公开(公告)号：US12001280B2

公开(公告)日：2024-06-04

申请号：US17133995

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Krishna K. Parat ,  Ravi H. Motwani ,  Rohit S. Shenoy ,  Ali Khakifirooz

IPC: G06F11/00 ,  G06F11/10 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04

CPC classification number: G06F11/1068 ,  G11C11/5621 ,  G11C16/26 ,  G11C16/0483

Abstract: Error correction coding (ECC) mis-corrected reads, if undetected, result in silent data corruption of a non-volatile memory device. Overcoming ECC mis-corrected reads is based on a read signature of a result of reading a page in the non-volatile memory device. An ECC mis-correct logic counts the number of bits in the end-most buckets into which the bits of the result is divided. End-most buckets that are overpopulated or starved reveal a tell-tale read signature of an ECC mis-correct. The ECC mis-correct is likely to occur when the read reference voltage level used to read the page is shifted in one direction or another to an extreme amount that risks reading data from a different page. Detecting ECC mis-corrected reads can be used to overcome the ECC mis-corrects and mitigate silent data corruption.

公开(公告)号：US11657889B2

公开(公告)日：2023-05-23

申请号：US16827235

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Richard L. Coulson ,  Zion S. Kwok ,  Ravi H. Motwani

IPC: G11C29/42 ,  G11C29/44 ,  G11C11/409 ,  G11C5/02 ,  G11C29/02 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C5/025 ,  G11C11/409 ,  G11C29/021 ,  G11C29/44 ,  G11C2029/1204

Abstract: Error correction values for a memory device include row error correction values and column error correction values for the same memory array. The memory device includes a memory array that is addressable in two spatial dimensions: a row dimension and a column dimension. The memory array is written as rows of data, and can be read as rows in the row dimension or read as columns in the column dimension. A data write triggers updates to row error correction values and to column error correction values.