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    TECHNIQUES TO SUPPORT MULITPLE INTERCONNECT PROTOCOLS FOR AN INTERCONNECT
    41.
    发明申请
    TECHNIQUES TO SUPPORT MULITPLE INTERCONNECT PROTOCOLS FOR AN INTERCONNECT 有权

    公开(公告)号：US20220197847A1

    公开(公告)日：2022-06-23

    申请号：US17674030

    申请日：2022-02-17

    Applicant: Intel Corporation

    Inventor： Stephen R. Van Doren ,  Rajesh M. Sankaran ,  David A. Koufaty ,  Ramacharan Sundararaman ,  Ishwar Agarwal

    IPC: G06F13/42 ,  G06F13/14

    Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to detect a message to communicate via an interconnect coupled with a device capable of communication via a plurality of interconnect protocols, the plurality of interconnect protocols comprising a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol. Embodiments also include determining an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message, and providing the message to a multi-protocol multiplexer coupled with the interconnect, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device.

    Coherent accelerator fabric controller
    42.
    发明授权
    Coherent accelerator fabric controller 有权

    公开(公告)号：US11263143B2

    公开(公告)日：2022-03-01

    申请号：US15720231

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Ritu Gupta ,  Aravindh V. Anantaraman ,  Stephen R. Van Doren ,  Ashok Jagannathan

    IPC: G06F12/00 ,  G06F12/0884 ,  G06F13/42

    Abstract: A fabric controller is provided for a coherent accelerator fabric. The coherent accelerator fabric includes a host interconnect, a memory interconnect, and an accelerator interconnect. The host interconnect communicatively couples to a host device. The memory interconnect communicatively couples to an accelerator memory. The accelerator interconnect communicatively couples to an accelerator having a last-level cache (LLC). An LLC controller is provided that is configured to provide a bias check for memory access operations on the fabric.

    PCIe controller with extensions to provide coherent memory mapping between accelerator memory and host memory
    43.
    发明授权
    PCIe controller with extensions to provide coherent memory mapping between accelerator memory and host memory 有权

    公开(公告)号：US11204867B2

    公开(公告)日：2021-12-21

    申请号：US15720648

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Ishwar Agarwal ,  Stephen R. Van Doren ,  Ramacharan Sundararaman

    IPC: G06F12/00 ,  G06F12/06

    Abstract: There is disclosed in an example a peripheral component interconnect express (PCIe) controller to provide coherent memory mapping between an accelerator memory and a host memory address space. The PCIe controller may include extensions to provide a coherent accelerator interconnect (CAI) to provide bias-based coherency tracking between the accelerator memory and the host memory address space. The extensions may include: a mapping engine to provide opcode mapping between PCIe instructions and on-chip system fabric (OSF) instructions for the CAI, a tunneling engine to provide scalable memory interconnect (SMI) tunneling of host memory operations to the accelerator memory via the CAI, host-bias-to-device-bias (HBDB) flip engine to enable the accelerator to flush a host cache line, and a QoS engine comprising a plurality of virtual channels.

    SPATIAL AND TEMPORAL MERGING OF REMOTE ATOMIC OPERATIONS
    45.
    发明申请
    SPATIAL AND TEMPORAL MERGING OF REMOTE ATOMIC OPERATIONS 审中-公开

    公开(公告)号：US20190205139A1

    公开(公告)日：2019-07-04

    申请号：US15858899

    申请日：2017-12-29

    Applicant: Intel Corporation

    Inventor： Christopher J. Hughes ,  Joseph Nuzman ,  Jonas Svennebring ,  Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  David A. Koufaty ,  Niall D. McDonnell ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  Stephen J. Robinson

    IPC: G06F9/30

    Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.

    ACCELERATOR FABRIC
    46.
    发明申请
    ACCELERATOR FABRIC 审中-公开

    公开(公告)号：US20190102311A1

    公开(公告)日：2019-04-04

    申请号：US15720231

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Ritu Gupta ,  Aravindh V. Anantaraman ,  Stephen R. Van Doren ,  Ashok Jagannathan

    IPC: G06F12/0884 ,  G06F13/42

    Abstract: A fabric controller to provide a coherent accelerator fabric, including: a host interconnect to communicatively couple to a host device; a memory interconnect to communicatively couple to an accelerator memory; an accelerator interconnect to communicatively couple to an accelerator having a last-level cache (LLC); and an LLC controller configured to provide a bias check for memory access operations.

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