公开(公告)号：US09495168B2

公开(公告)日：2016-11-15

申请号：US14126466

申请日：2013-05-30

Applicant: Intel Corporation

Inventor： Hongbo Rong ,  Cheng Wang ,  Hyunchul Park ,  Youfeng Wu

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/30 ,  G06F9/45

CPC classification number: G06F9/3838 ,  G06F8/434 ,  G06F8/441 ,  G06F8/443 ,  G06F9/30127 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/384

Abstract: In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，系统包括处理器，其包括一个或多个核和多个别名寄存器，用于存储与循环的多个操作相关联的存储器范围信息。 存储器范围信息引用存储器内的一个或多个存储器位置。 该系统还包括寄存器分配装置，用于将每个别名寄存器分配给循环的对应操作，其中根据旋转调度进行分配，并且在第一次迭代中将一个别名寄存器分配给第一操作 循环和循环的后续迭代中的第二操作。 该系统还包括耦合到处理器的存储器。 描述和要求保护其他实施例。

公开(公告)号：US09342303B2

公开(公告)日：2016-05-17

申请号：US13843940

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： James E. Smith ,  Denis M. Khartikov ,  Shiliang Hu ,  Youfeng Wu

IPC: G06F9/30 ,  G06F9/45

CPC classification number: G06F9/30 ,  G06F8/443 ,  G06F9/30181 ,  G06F9/328

Abstract: A system and method to enhance execution of architected instructions in a processor uses auxiliary code to optimize execution of base microcode. An execution context of the architected instructions may be profiled to detect potential optimizations, resulting in generation and storage of auxiliary microcode. When the architected instructions are decoded to base microcode for execution, the base microcode may be enhanced or modified using retrieved auxiliary code.

Abstract translation: 用于增强处理器中的架构指令执行的系统和方法使用辅助代码来优化基本微代码的执行。 可以对构建的指令的执行上下文进行分析以检测潜在的优化，从而产生和存储辅助微代码。 当结构化指令被解码为基本微代码以执行时，可以使用检索的辅助代码来增强或修改基本微代码。

公开(公告)号：US20160092285A1

公开(公告)日：2016-03-31

申请号：US14497157

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Albert Hartono ,  Nalini Vasudevan ,  Sara S. Baghsorkhi ,  Cheng Wang ,  Youfeng Wu

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F8/452 ,  G06F9/4552

Abstract: A computer-implemented method for managing loop code in a compiler includes using a conflict detection procedure that detects across-iteration dependency for arrays of single memory addresses to determine whether a potential across-iteration dependency exists for arrays of memory addresses for ranges of memory accessed by the loop code.

Abstract translation: 用于管理编译器中的循环代码的计算机实现的方法包括使用冲突检测过程，其检测单个存储器地址的阵列的跨迭代依赖性，以确定存储器地址范围内的存储器地址的阵列是否存在潜在的跨迭代依赖性 通过循环代码。

公开(公告)号：US20160092223A1

公开(公告)日：2016-03-31

申请号：US14498178

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Cheng Wang ,  Youfeng Wu ,  Rajesh M Sankaran

IPC: G06F9/30 ,  G06F12/08 ,  G06F9/38

Abstract: A processor of an aspect includes a decode unit to decode a persistent store fence instruction. The processor also includes a memory subsystem module coupled with the decode unit. The memory subsystem module, in response to the persistent store fence instruction, is to ensure that a given data corresponding to the persistent store fence instruction is stored persistently in a persistent storage before data of all subsequent store instructions is stored persistently in the persistent storage. The subsequent store instructions occur after the persistent store fence instruction in original program order. Other processors, methods, systems, and articles of manufacture are also disclosed.

Abstract translation: 一方面的处理器包括解码单元，用于解码持久存储栏指令。 处理器还包括与解码单元耦合的存储器子系统模块。 存储器子系统模块响应于永久存储围栏指令，确保在持久存储指令的数据被持久地存储在永久存储器中之前，与永久存储围栏指令相对应的给定数据被永久地存储在持久存储器中。 随后的存储指令发生在原始程序顺序中的持久存储栏指令之后。 还公开了其它处理器，方法，系统和制品。

公开(公告)号：US10534424B2

公开(公告)日：2020-01-14

申请号：US14986676

申请日：2016-01-02

Applicant: Intel Corporation

Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC: G06F1/329 ,  G06F1/3287 ,  G06F9/38 ,  G06F9/50 ,  G06F11/34 ,  G06F9/445 ,  G06F9/48

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

公开(公告)号：US10296343B2

公开(公告)日：2019-05-21

申请号：US15474666

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Jason M. Agron ,  Youfeng Wu

IPC: G06F9/44 ,  G06F9/52 ,  G06F12/08 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F9/46

Abstract: A processing device including a first shadow register, a second shadow register, and an instruction execution circuit, communicatively coupled to the first shadow register and the second shadow register, to receive a sequence of instructions comprising a first local commit marker, a first global commit marker, and a first register access instruction referencing an architectural register, speculatively execute the first register access instruction to generate a speculative register state value associated with a physical register, responsive to identifying the first local commit marker, store, in the first shadow register, the speculative register state value, and responsive to identifying the first global commit marker, store, in the second shadow register, the speculative register state value.

公开(公告)号：US10268497B2

公开(公告)日：2019-04-23

申请号：US14126894

申请日：2013-10-24

Applicant: Intel Corporation

Inventor： Hongbo Rong ,  Hyunchul Park ,  Cheng Wang ,  Youfeng Wu

IPC: G06F9/455 ,  G06F8/41 ,  G06F8/52

Abstract: Methods and apparatus relating to conjugate code generation for efficient dynamic optimizations are described. In an embodiment, a binary code and an intermediate representation (IR) code are generated based at least partially on a source program. The binary code and the intermediate code are transmitted to a virtual machine logic. The binary code and the IR code each include a plurality of regions that are in one-to-one correspondence. Other embodiments are also claimed and described.

公开(公告)号：US10191745B2

公开(公告)日：2019-01-29

申请号：US15475389

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Hou-Jen Ko ,  Girish Venkatasubramanian ,  Jason Agron ,  Tyler Sondag ,  Youfeng Wu

IPC: G06F9/45 ,  G06F9/30

Abstract: In one example a processor includes a region formation engine to identify a region of code for translation from a guest instruction set architecture to a native instruction set architecture. The processor also includes a binary translator to translate the region of code. The region formation engine is to perform aggressive region formation, which includes forming a region across a boundary of a return instruction. The translated region of code is to prevent a side entry into the translated region of code at a translated return target instruction included in the translated region of code. In more specific examples, performing aggressive region formation includes a region formation grow phase and a region formation cleanup phase. In the grow phase priority may be given to growing complete paths from a call target to a corresponding return. The region formation cleanup phase may comprise eliminating call targets that are not reachable.

公开(公告)号：US10120686B2

公开(公告)日：2018-11-06

申请号：US15175899

申请日：2016-06-07

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Oleg Margulis ,  Ching-Tsun Chou ,  Youfeng Wu

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

Abstract: A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, mark the start and end of a region of the instruction stream with the redundant store, remove the redundant store, and store an amended instruction stream with the redundant store removed.

公开(公告)号：US20180285112A1

公开(公告)日：2018-10-04

申请号：US15474666

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Jason M. Agron ,  Youfeng Wu

IPC: G06F9/30 ,  G06F12/0875 ,  G06F9/38

CPC classification number: G06F9/30174 ,  G06F9/30101 ,  G06F9/3842 ,  G06F9/467 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/507

Abstract: A processing device including a first shadow register, a second shadow register, and an instruction execution circuit, communicatively coupled to the first shadow register and the second shadow register, to receive a sequence of instructions comprising a first local commit marker, a first global commit marker, and a first register access instruction referencing an architectural register, speculatively execute the first register access instruction to generate a speculative register state value associated with a physical register, responsive to identifying the first local commit marker, store, in the first shadow register, the speculative register state value, and responsive to identifying the first global commit marker, store, in the second shadow register, the speculative register state value.