公开(公告)号：US20130071990A1

公开(公告)日：2013-03-21

申请号：US13677126

申请日：2012-11-14

Applicant: Intermolecular, Inc.

Inventor： Imran Hashim ,  Hanhong Chen ,  Tony Chiang ,  Indranil De ,  Nobi Fuchigami ,  Edward Haywood ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC: H01L21/02

CPC classification number: H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

Abstract translation: 本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺作为反应过程的结果来生产氧化物层 反应。

公开(公告)号：US20130069202A1

公开(公告)日：2013-03-21

申请号：US13677536

申请日：2012-11-15

Applicant: INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC

Inventor： Xiangxin Rui ,  Takashi Arao ,  Hanhong Chen ,  Naonori Fujiwara ,  Edward Haywood ,  Toshiyuki Hirota ,  Takakazu Kiyomura ,  Kenichi Koyanagi ,  Sandra G. Malhotra

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L21/02 ,  H01L27/1085 ,  H01L28/40

Abstract: A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO2) on the first TiN electrode; depositing a dielectric material on the first layer of titanium dioxide; and depositing a second TiN electrode on the dielectric material.

公开(公告)号：US20130069201A1

公开(公告)日：2013-03-21

申请号：US13675971

申请日：2012-11-13

Applicant: Intermolecular, Inc.

Inventor： Imran Hashim ,  Hanhong Chen ,  Tony Chiang ,  Indranil De ,  Nobumichi Fuchigami ,  Edward Haywood ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC: H01L49/02

CPC classification number: H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

公开(公告)号：US20130044404A1

公开(公告)日：2013-02-21

申请号：US13657782

申请日：2012-10-22

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Nobumichi Fuchigami ,  Imran Hashim ,  Edward L. Haywood ,  Pragati KUMAR ,  Sandra G. Malhotra ,  Monica Sawkar Mathur ,  Prashant B. Phatak ,  Sunil Shanker

IPC: H01G4/30 ,  H01G4/018

CPC classification number: H01G4/1218 ,  C23C16/405 ,  C23C16/45531 ,  C23C16/56 ,  H01G4/33 ,  H01L21/02186 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02312 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3142 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.

Abstract translation: 本公开内容提供（a）制造基于氧化钛的氧化物层（例如电介质层）的方法，以抑制锐钛矿相氧化钛的形成和（b）相关的器件和结构。 使用底部电极（或其他基底）的臭氧预处理随后进行ALD工艺形成金属 - 绝缘体 - 金属（MIM）堆叠，以形成使用含酰胺前体的TiO 2电介质。 在ALD工艺之后，氧化退火工艺的应用热度足以愈合TiO2电介质中的缺陷，并降低TiO2和电极之间的界面态; 选择退火温度以使其不那么热，以致破坏BEL表面粗糙度。 进一步的工艺变型可以包括在ALD工艺期间掺杂氧化钛，基座加热至275-300摄氏度，对于BEL使用铂或钌，对于每个ALD工艺循环使用多个试剂脉冲的臭氧。 该方法提供高沉积速率，并且所得MIM结构基本上没有与锐钛矿相氧化钛相关的x射线衍射峰。

公开(公告)号：US09178006B2

公开(公告)日：2015-11-03

申请号：US14177118

申请日：2014-02-10

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Xiangxin Rui ,  Hanhong Chen ,  Naonori Fujiwara ,  Imran Hashim ,  Kenichi Koyanagi

IPC: H01L49/02 ,  H01L27/108 ,  H01G4/10

CPC classification number: H01L28/40 ,  H01G4/10 ,  H01G4/1236 ,  H01G4/33 ,  H01L27/10805 ,  H01L27/1085 ,  H01L28/56 ,  H01L28/75

Abstract: A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly-doped or non-doped material. The highly doped material will remain amorphous (

Abstract translation: 用于减少DRAM MIM电容器中的漏电流的方法包括从非晶高掺杂材料，非晶高带隙材料和轻掺杂或非掺杂材料形成多层电介质叠层。 退火步骤后，高掺杂材料将保持无定形（<30％结晶）。 在退火步骤之后，高带隙材料将保持无定形（<30％结晶）。 在退火步骤之后，轻掺杂或非掺杂材料将变成晶体（≥30％结晶）。 高带隙材料形成在无定形高掺杂材料和轻掺杂材料和非掺杂材料之间，并提供通过多层电介质叠层的导电的中间屏障。

公开(公告)号：US09082782B2

公开(公告)日：2015-07-14

申请号：US13655653

申请日：2012-10-19

Applicant: Intermolecular Inc.

Inventor： Hanhong Chen ,  Toshiyuki Hirota ,  Pragati Kumar ,  Xiangxin Rui ,  Sunil Shanker

IPC: H01L29/02 ,  H01L49/02 ,  C23C16/40 ,  H01L27/108

CPC classification number: H01L28/60 ,  C23C16/405 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

公开(公告)号：US20150087130A1

公开(公告)日：2015-03-26

申请号：US14033326

申请日：2013-09-20

Applicant: Elpida Memory, Inc ,  Intermolecular, Inc.

Inventor： Hanhong Chen ,  David Chi ,  Imran Hashim ,  Mitsuhiro Horikawa ,  Sandra G. Malhotra

IPC: H01L49/02

CPC classification number: H01L28/56 ,  H01L27/108 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/75 ,  H01L28/82

Abstract: A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.

Abstract translation: 形成电容器堆叠的方法包括形成包括导电金属氮化物材料的第一底部电极层。 在第一底部电极层的上方形成第二底部电极层。 第二底部电极层包括导电金属氧化物材料，其中导电金属氧化物材料的晶体结构促进随后沉积的介电层的期望的高k结晶相。 在第二底部电极层的上方形成电介质层。 任选地，在介电层上方形成富氧金属氧化物层。 可选地，在富氧金属氧化物层的上方形成第三上电极层。 第三顶部电极层包括导电金属氧化物材料。 第四上电极层形成在第三顶电极层的上方。 第四顶部电极层包括导电金属氮化物材料。

公开(公告)号：US08900418B2

公开(公告)日：2014-12-02

申请号：US13677126

申请日：2012-11-14

Applicant: Intermolecular, Inc.

Inventor： Imran Hashim ,  Hanhong Chen ,  Tony Chiang ,  Indranil De ,  Nobi Fuchigami ,  Edward Haywood ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC: C23C14/34 ,  B05D5/12 ,  H01L49/02 ,  C23C16/40 ,  C23C16/455 ,  H01L21/314 ,  H01L21/316 ,  H01L27/108 ,  H01L21/02

CPC classification number: H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

Abstract translation: 本公开内容提供（a）制造基于钇和钛的氧化物层（例如电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层 反应。

公开(公告)号：US08859301B2

公开(公告)日：2014-10-14

申请号：US13914848

申请日：2013-06-11

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Edward Haywood ,  Pragati Kumar

IPC: G01R31/26 ,  H01L21/66 ,  G01N23/223

CPC classification number: G01N23/223 ,  H01L22/12

Abstract: Determining an unknown step coverage of a thin film deposited on a 3D wafer includes exposing a planar wafer comprising a first film deposited thereon to X-ray radiation to create first fluorescent radiation; detecting the first fluorescent radiation; measuring a number of XRF counts on the planar wafer; creating an XRF model of the planar wafer; providing a portion of the 3D wafer comprising troughs and a second film deposited thereon; determining a multiplier factor between the portion of the 3D wafer and the planar wafer; exposing the portion of the 3D wafer to X-ray radiation to create second fluorescent radiation; detecting the second fluorescent radiation; measuring a number of XRF counts on the portion of the 3D wafer; calculating a step coverage of the portion of the 3D wafer; and determining a uniformity of the 3D wafer based on the step coverage of the portion of the 3D wafer.

Abstract translation: 确定沉积在3D晶片上的薄膜的未知步骤覆盖包括将包括沉积在其上的第一膜的平面晶片暴露于X射线辐射以产生第一荧光辐射; 检测第一荧光辐射; 测量平面晶片上的XRF数量; 创建平面晶片的XRF模型; 提供包括槽的3D晶片的一部分和沉积在其上的第二膜; 确定所述3D晶片的所述部分和所述平面晶片之间的乘数; 将3D晶片的部分暴露于X射线辐射以产生第二荧光辐射; 检测第二荧光辐射; 测量3D晶片部分上的XRF数量; 计算3D晶片的部分的台阶覆盖; 以及基于所述3D晶片的所述部分的台阶覆盖来确定所述3D晶片的均匀性。

公开(公告)号：US08737036B2

公开(公告)日：2014-05-27

申请号：US13657782

申请日：2012-10-22

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Nobumichi Fuchigami ,  Imran Hashim ,  Edward L. Haywood ,  Pragati Kumar ,  Sandra G. Malhotra ,  Monica Sawkar Mathur ,  Prashant B. Phatak ,  Sunil Shanker

IPC: H01G4/30

CPC classification number: H01G4/1218 ,  C23C16/405 ,  C23C16/45531 ,  C23C16/56 ,  H01G4/33 ,  H01L21/02186 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02312 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3142 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.

Abstract translation: 本公开内容提供（a）制造基于氧化钛的氧化物层（例如电介质层）的方法，以抑制锐钛矿相氧化钛的形成和（b）相关的器件和结构。 使用底部电极（或其他基底）的臭氧预处理随后进行ALD工艺来形成金属 - 绝缘体 - 金属（“MIM”）堆叠，以形成根植于使用含酰胺的前体的TiO 2电介质。 在ALD工艺之后，氧化退火工艺的应用热度足以愈合TiO2电介质中的缺陷，并降低TiO2和电极之间的界面态; 选择退火温度以使其不那么热，以致破坏BEL表面粗糙度。 进一步的工艺变型可以包括在ALD工艺期间掺杂氧化钛，基座加热至275-300摄氏度，对于BEL使用铂或钌，对于每个ALD工艺循环使用多个试剂脉冲的臭氧。 该方法提供高沉积速率，并且所得MIM结构基本上没有与锐钛矿相氧化钛相关的x射线衍射峰。