公开(公告)号：US20230077760A1

公开(公告)日：2023-03-16

申请号：US17474222

申请日：2021-09-14

Applicant: International Business Machines Corporation

Inventor： Koichi Motoyama ,  Kenneth Chun Kuen Cheng ,  Chanro Park ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A high modulus material layer is formed on a conductive stack. A trench is formed that exposes a surface of the liner and filled with metal. The metal is patterned to form interconnect lines and vias. The high modulus material is removed. A conformal layer is formed on exposed surfaces of the stack and the interconnect lines and vias. A low-κ dielectric is formed on the conformal layer such that the low-κ dielectric is of a height coplanar with the top surface of the vias. The conformal layer is removed from a top surface of the vias. A next level metal layer is formed on the top surface of the vias and low-κ dielectric layer such that added vias of the next level metal layer are directly on the top surface of the vias.

公开(公告)号：US11600325B2

公开(公告)日：2023-03-07

申请号：US17109296

申请日：2020-12-02

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung Chen ,  Mary Claire Silvestre ,  Soon-Cheon Seo ,  Chi-Chun Liu ,  Fee Li Lie ,  Chih-Chao Yang ,  Yann Mignot ,  Theodorus E. Standaert

IPC: G11C11/08 ,  G11C13/00 ,  G11C11/16 ,  H03K19/20

Abstract: A resistance switching RAM logic device is presented. The device includes a pair of resistance switching RAM cells that may be independently programed into at least a low resistance state (LRS) or a high resistance state (HRS). The resistance switching RAM logic device may further include a shared output node electrically connected to the pair of resistance switching RAM cells. A logical output may be determined from the programmed resistance state of each of the resistance switching RAM cells.

公开(公告)号：US20220384564A1

公开(公告)日：2022-12-01

申请号：US17303390

申请日：2021-05-27

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung Chen ,  Chih-Chao Yang

IPC: H01L49/02 ,  H01G4/005 ,  H01G4/10

Abstract: An interdigitated metal-insulator-metal capacitor structure is formed by a first unitary body of a first conductive material that includes a first metal plate, a first set of interdigitated electrodes protruding upwards from a top surface of the first metal plate, and a first set of connecting vias protruding downwards from a bottom surface of the first metal plate. A second unitary body of a second conductive material is disposed above the first unitary body and electrically separated from the first unitary body by an insulating layer. The second unitary body includes a second metal plate, a second set of interdigitated electrodes protruding downwards from a bottom surface of the second metal plate, and a second set of connecting vias protruding upwards from a top surface of the second metal plate. The first set of interdigitated electrodes are interleaved with the second set of interdigitated electrodes.

公开(公告)号：US20220359814A1

公开(公告)日：2022-11-10

申请号：US17313403

申请日：2021-05-06

Applicant: International Business Machines Corporation

Inventor： Theodorus E. Standaert ,  Daniel Charles Edelstein ,  Chih-Chao Yang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08

Abstract: A semiconductor structure forms two or more tightly pitched memory devices using a dielectric material for a gap fill material. The approach includes providing two adjacent bottom electrodes in a layer of an insulating material and above a metal layer. Two adjacent pillars are each above one of the two adjacent bottom electrodes where each pillar of the two adjacent pillars is composed of a stack of materials for a memory device. A spacer is around the vertical sides each of the two adjacent pillars. The dielectric material is on the spacer around the vertical sides each of the two adjacent pillars, on the layer of the insulating material between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of a gap between the two adjacent pillars. A low k material covers the dielectric material and exposed portions of the layer of the insulating material.

公开(公告)号：US11302639B2

公开(公告)日：2022-04-12

申请号：US16744960

申请日：2020-01-16

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Baozhen Li ,  Ashim Dutta

IPC: H01L23/532 ,  H01L23/522 ,  H01L43/08 ,  H01L27/11597 ,  H01L45/00 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01L27/24

Abstract: Re-depositing of metal-containing particles of an embedded electrically conductive structure onto sidewalls of an overlying metal-containing structure is alleviated in the present application by providing a pedestal structure between the embedded electrically conductive structure and the metal-containing structure, wherein the pedestal structure has a flared sidewall that extends beyond a perimeter of the embedded electrically conductive structure. Such a pedestal structure (which can be referred to herein as a footing flare pedestal structure) mitigates, and in some embodiments, entirely eliminates, the exposure of the embedded electrically conductive structure during the patterning of metal-containing layers formed atop the embedded electrically conductive structure.

公开(公告)号：US11289375B2

公开(公告)日：2022-03-29

申请号：US16826566

申请日：2020-03-23

Applicant: International Business Machines Corporation

Inventor： Chanro Park ,  Kenneth Chun Kuen Cheng ,  Koichi Motoyama ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L23/532

Abstract: Interconnect structures and methods for forming the interconnect structures generally include forming a dielectric layer over a substrate. The dielectric layer includes a dielectric layer top surface. A metal line is formed in the dielectric layer. The metal line includes a sacrificial upper region and a lower region. The sacrificial upper region is formed separately from the lower region and the lower region includes a lower region top surface positioned below the dielectric layer top surface. The sacrificial upper region is removed, thereby exposing the lower region top surface and forming a trench defined by the lower region top surface and sidewalls of the dielectric layer. An interconnect structure is deposited such that at least a portion of the interconnect structure fills the trench, thereby defining a fully aligned top via.

公开(公告)号：US20220093453A1

公开(公告)日：2022-03-24

申请号：US17541450

申请日：2021-12-03

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Terry A. Spooner ,  Koichi Motoyama ,  Shyng-Tsong Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Back end of line metallization structures and methods for fabricating self-aligned vias. The structures generally include a first interconnect structure disposed above a substrate. The first interconnect structure includes a metal line formed in a first interlayer dielectric. A second interconnect structure overlies the first interconnect structure. The second interconnect structure includes a second cap layer on the first interlayer dielectric, a second interlayer dielectric thereon, and at least one self-aligned via in the second interlayer dielectric conductively coupled to at least a portion of the metal line of the first interconnect structure, wherein any misalignment of the at least one self-aligned via results in the at least one self-aligned via landing on both the metal line of the first interconnect structure and the second cap layer. The second cap layer is an insulating material.

公开(公告)号：US11270935B2

公开(公告)日：2022-03-08

申请号：US16515926

申请日：2019-07-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Chih-Chao Yang ,  Jing Guo

IPC: H01L23/522 ,  H01L21/768

Abstract: A method of forming cut conductive lines is provided. The method includes forming a trough in a dielectric cover layer over a plurality of electrical contacts. The method further includes filling the trough with a planarization layer, and forming a plurality of vias in the planarization layer and the dielectric cover layer, wherein each of the plurality of vias is aligned with one of the plurality of electrical contacts. The method further includes removing the planarization layer, and forming a sacrificial via plug in each of the plurality of vias in the dielectric cover layer. The method further includes forming a fill layer in the trough, and forming a planarization layer opening through the fill layer, wherein the planarization layer opening is positioned between two adjacent sacrificial via plugs. The method further includes forming a separator in the planarization layer opening.

公开(公告)号：US11244907B2

公开(公告)日：2022-02-08

申请号：US16732531

申请日：2020-01-02

Applicant: International Business Machines Corporation

Inventor： Tianji Zhou ,  Saumya Sharma ,  Dominik Metzler ,  Chih-Chao Yang ,  Theodorus E. Standaert

IPC: H01L23/544 ,  G03F9/00

Abstract: Methods and structures for improving alignment contrast for patterning a metal layer generally includes depositing a metal layer having a plurality of grains, wherein grain boundaries between the grains forms grooves at a surface of the metal layer. The metal layer is subjected to surface treatment to form an oxide or a nitride layer and fill the surface grooves. The metal layer can be patterned using alignment marks in the metal layer and/or underlying layers. Filling the grooves with the oxide or nitride increases alignment contrast relative to patterning the metal layer without the surface treating.

公开(公告)号：US11201112B2

公开(公告)日：2021-12-14

申请号：US16748951

申请日：2020-01-22

Applicant: International Business Machines Corporation

Inventor： Kenneth Chun Kuen Cheng ,  Chanro Park ,  Koichi Motoyama ,  Chih-Chao Yang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: An interconnect structure includes a first electrically conductive via portion on an upper surface of a substrate, the first electrically conductive via elongated along a first direction, and a first ILD material on the substrate and covering the first electrically conductive via portion. The first ILD material includes an ILD upper surface exposing a via surface of the first electrically conductive via portion. A second electrically conductive via portion is on the ILD upper surface and the via upper surface thereby defining a contact area between the first electrically conductive via portion and the second electrically conductive via portion. The second electrically conductive via portion elongated along a second direction orthogonal with respect to the first direction. A second ILD material is on the ILD upper surface to cover the second electrically conductive via portion. The first and second electrically conductive via portions are fully aligned at the contact area.