公开(公告)号：US20200243681A1

公开(公告)日：2020-07-30

申请号：US16845350

申请日：2020-04-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  Juntao Li ,  Shogo Mochizuki

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/04 ,  H01L29/423 ,  H01L29/06 ,  H01L29/161

Abstract: A method of forming a semiconductor device that includes forming at least two semiconductor fin structures having sidewalls with {100} crystalline planes that is present atop a supporting substrate; and epitaxially growing a source/drain region in a lateral direction from the sidewalls of each fin structure. The second source/drain regions have substantially planar sidewalls. A metal wrap around electrode is formed on an upper surface and the substantially planar sidewalls of the source/drain regions. Air gaps are formed between the source/drain regions of the at least two semiconductor fin structures.

公开(公告)号：US10720527B2

公开(公告)日：2020-07-21

申请号：US15861127

申请日：2018-01-03

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Peng Xu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/16

Abstract: Embodiments of the invention are directed to a semiconductor device that includes a substrate formed from a first type of semiconductor material, along with a fin formed on the substrate. The fin includes a fin channel region configured to include a bottom region, a central region, and a top active region. The central region includes a dielectric material and couples the bottom region to the top active region. The top active region includes a second type of semiconductor material, and the bottom region includes a third type of semiconductor material.

公开(公告)号：US20200227633A1

公开(公告)日：2020-07-16

申请号：US16835843

申请日：2020-03-31

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Peng Xu

IPC: H01L45/00 ,  H01L27/24

Abstract: Techniques for fabricating a volatile memory structure having a transistor and a memory component is described. The volatile memory structure comprises the memory component formed on a substrate, wherein a first shape comprising one or more pointed edges is formed on a first surface of the memory component. The volatile memory structure further comprises transistor formed on the substrate and electrically coupled to the memory component to share operating voltage, wherein operating voltage applied to the transistor flows to the memory component.

公开(公告)号：US20200152762A1

公开(公告)日：2020-05-14

申请号：US16746523

申请日：2020-01-17

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Choonghyun Lee ,  SangHoon Shin ,  Jingyun Zhang ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/51 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/786

Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by forming a gradient threshold voltage adjusting gate dielectric structure between the bottom drain region of the FET and the top source region of the FET. The gradient threshold voltage adjusting gate dielectric structure includes a doped interface high-k gate dielectric material that is located in proximity to the bottom drain region and a non-doped high-k dielectric material that is located in proximity to the top source region. The non-doped high-k dielectric material has a higher threshold voltage than the doped interface high-k gate dielectric.

公开(公告)号：US20200152755A1

公开(公告)日：2020-05-14

申请号：US16745148

申请日：2020-01-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Seyoung Kim ,  Injo Ok ,  Soon-Cheon Seo

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/732 ,  H01L29/08 ,  H01L29/417 ,  H01L21/768 ,  H01L29/737

Abstract: A bipolar junction transistor includes a collector having a first surface on a first level and a second surface on a second level. A base is formed on the second level of the collector, and an emitter is formed on the base. A dielectric liner is formed on vertical sidewalls of the collector, the base and the emitter and over the first surface. A conductive region is formed adjacent to the base in the dielectric liner. A base contact is formed along one of the vertical sidewalls to connect to the base through the conductive region.

公开(公告)号：US20200152524A1

公开(公告)日：2020-05-14

申请号：US16738756

申请日：2020-01-09

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  Juntao Li

IPC: H01L21/84 ,  H01L29/786 ,  H01L29/66 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/51 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/8234

Abstract: Techniques for reducing work function metal variability along the channel of VFET devices are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming bottom source/drains at a base of the fins and bottom spacers on the bottom source/drains; forming gate stacks over the fins including a gate conductor having a combination of work function metals including an outer layer and at least one inner layer of the work function metals; isotropically etching the work function metals which recesses the gate stacks with an outwardly downward sloping profile; isotropically etching the at least one inner layer while covering the outer layer of the work function metals to eliminate the outwardly downward sloping profile of the gate stacks; forming top spacers above the gate stacks; and forming top source and drains at tops of the fins. A VTFET device is also provided.

公开(公告)号：US20200127054A1

公开(公告)日：2020-04-23

申请号：US16167099

申请日：2018-10-22

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Alexander Reznicek ,  Choonghyun Lee ,  Jingyun Zhang

IPC: H01L27/24 ,  G06N3/063 ,  H01L45/00

Abstract: Techniques regarding FET 1T2R unit cells are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a first resistive random-access memory unit operably coupled to a field-effect transistor by a first extrinsic semiconductor layer. The system can also comprise a second resistive random-access memory unit operably coupled to the field-effect transistor by a second extrinsic semiconductor layer.

公开(公告)号：US10600889B2

公开(公告)日：2020-03-24

申请号：US15852111

申请日：2017-12-22

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Peng Xu

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775

Abstract: A semiconductor structure is provided which includes a nanosheet stack structure on a base. The nanosheet stack structure includes a multilayered nanosheet between adjacent nanosheet layers. The multilayered nanosheet includes one or more first layers of a first material and one or more second layers of a second material, wherein the first material has an etch selectivity different than the second material. The one or more first layers of the multilayered nanosheet are recessed. A first inner spacer includes a third material is formed by depositing the third material into an outer portion of the one or more recessed first layers of the multilayered nanosheet. The one or more second layers of the multilayered nanosheet are recessed. A second inner spacer includes a fourth material which is formed by depositing the fourth material into an outer portion of the one or more recessed second layers of the first multilayered nanosheet.

公开(公告)号：US10600885B2

公开(公告)日：2020-03-24

申请号：US16105442

申请日：2018-08-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Juntao Li ,  Choonghyun Lee ,  Shogo Mochizuki

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: A method of forming a fin field effect transistor device is provided. The method includes forming a plurality of vertical fins on a substrate. The method further includes forming a bottom source/drain layer adjacent to the plurality of vertical fins, and growing a doped layer on the bottom source/drain layer and sidewalls of the plurality of vertical fins. The method further includes forming a dummy gate liner on the doped layer and the bottom source/drain layer, and forming a dummy gate fill on the dummy gate liner. The method further includes forming a protective cap layer on the dummy gate fill, and removing a portion of the protective cap layer to expose a top surface of the plurality of vertical fins.

公开(公告)号：US20200091342A1

公开(公告)日：2020-03-19

申请号：US16703304

申请日：2019-12-04

Applicant: International Business Machines Corporation

Inventor： Injo Ok ,  Choonghyun Lee ,  Soon-Cheon Seo ,  Seyoung Kim

IPC: H01L29/78 ,  H01L27/07 ,  H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/66 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417

Abstract: Techniques related to a boosted vertical field effect transistor and method of fabricating the same are provided. A logic device can comprise a vertical field effect transistor comprising a substrate, a first epitaxial layer and a second epitaxial layer. A bottom source/drain contact can be between a top surface and the first epitaxial layer and a top source/drain contact can be between the top surface and the second epitaxial layer at respective first portions of one or more vertical fins. The logic device can also comprise a boosted bipolar junction transistor. A bipolar junction transistor contact can be between the top surface and the second epitaxial layer at respective second portions of the one or more vertical fins. The respective first portions and the respective second portions can be opposite portions of the one or more vertical fins.