公开(公告)号：US10985025B2

公开(公告)日：2021-04-20

申请号：US16173331

申请日：2018-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric R. Miller ,  Stuart A. Sieg ,  Yann Mignot ,  Indira Seshadri ,  Christopher J. Waskiewicz

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/033 ,  H01L29/66

Abstract: Methods for forming semiconductor fins include forming a protective layer around a base of a hardmask fin on an underlying semiconductor layer. A portion of the hardmask fin is etched away with an etch that is selective to the protective layer. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.

公开(公告)号：US10833172B2

公开(公告)日：2020-11-10

申请号：US16104230

申请日：2018-08-17

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Christopher J. Waskiewicz ,  Miaomiao Wang ,  Hemanth Jagannathan

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/08 ,  H01L21/265 ,  H01L21/3213

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin. A first source/drain contacts the semiconductor fin. An interfacial layer contacts sidewalls of the semiconductor fin. An insulating layer contacts the interfacial layer. One or more conductive gate layers encapsulate the interfacial and insulating layers. A second source/drain is formed above the first source/drain. The method comprises forming at least one semiconductor fin. An interfacial layer is formed in contact with sidewalls of the semiconductor fin. An insulating layer is formed in contact with the interfacial layer. The interfacial layer and the insulating layer are encapsulated by one or more conductive gate layers.

公开(公告)号：US20200135570A1

公开(公告)日：2020-04-30

申请号：US16173378

申请日：2018-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric R. Miller ,  Stuart A. Sieg ,  Yann Mignot ,  Indira Seshadri ,  Christopher J. Waskiewicz

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/033 ,  H01L27/088 ,  H01L29/66

Abstract: Methods for forming semiconductor fins include forming a sacrificial semiconductor structure around a hardmask fin on an underlying semiconductor layer. A first etch is performed that partially etches away a portion of the hardmask fin and the sacrificial semiconductor structure with a first etch chemistry. A second etch is performed that etches away remaining material of the portion of the hardmask fin and partially etches remaining material of the sacrificial semiconductor structure with a second etch chemistry. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.

公开(公告)号：US20180342458A1

公开(公告)日：2018-11-29

申请号：US16053282

申请日：2018-08-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marc A. Bergendahl ,  James J. Demarest ,  Christopher J. Penny ,  Christopher J. Waskiewicz

IPC: H01L23/525 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5256 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295

Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.

公开(公告)号：US20170243821A1

公开(公告)日：2017-08-24

申请号：US15358701

申请日：2016-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marc A. Bergendahl ,  James J. Demarest ,  Christopher J. Penny ,  Christopher J. Waskiewicz

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5256 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295

Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.

公开(公告)号：US20170141030A1

公开(公告)日：2017-05-18

申请号：US15160546

申请日：2016-05-20

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  James J. Demarest ,  Christopher J. Penny ,  Christopher J. Waskiewicz

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/0276 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

Abstract: A technique relates to an airgap structure. A dielectric layer is formed on an underlying layer. Copper filled trenches are formed in the dielectric layer, and a metal liner lines the copper filled trenches. An oxide liner lines the metal liner and covers the dielectric layer. One or more airgaps are formed between the copper filled trenches in areas in which the oxide liner was not present on the dielectric layer. A cap layer is formed on top of the one or more airgaps, the copper filled trenches, and portions of the oxide liner.

公开(公告)号：US08986921B2

公开(公告)日：2015-03-24

申请号：US13741611

申请日：2013-01-15

Applicant: International Business Machines Corporation

Inventor： Daniel C. Edelstein ,  Bryan G. Morris ,  Tuan A. Vo ,  Christopher J. Waskiewicz ,  Yunpeng Yin

IPC: G03F7/00 ,  H01L21/00 ,  H01L21/311 ,  H01L21/302 ,  G03F7/09

CPC classification number: G03F7/094

Abstract: A lithographic material stack including a metal-compound hard mask layer is provided. The lithographic material stack includes a lower organic planarizing layer (OPL), a dielectric hard mask layer, and the metal-compound hard mask layer, an upper OPL, an optional anti-reflective coating (ARC) layer, and a photoresist layer. The metal-compound hard mask layer does not attenuate optical signals from lithographic alignment marks in underlying material layers, and can facilitate alignment between different levels in semiconductor manufacturing.

Abstract translation: 提供了包括金属化合物硬掩模层的平版印刷材料堆叠。 平版印刷材料堆叠包括下部有机平坦化层（OPL），电介质硬掩模层和金属化合物硬掩模层，上部OPL，可选的抗反射涂层（ARC）层和光致抗蚀剂层。 金属化合物硬掩模层不会使光信号从下面的材料层中的光刻对准标记衰减，并且可以促进半导体制造中的不同层次之间的对准。

公开(公告)号：US12249643B2

公开(公告)日：2025-03-11

申请号：US17482940

申请日：2021-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andrew Gaul ,  Julien Frougier ,  Ruilong Xie ,  Andrew M. Greene ,  Christopher J. Waskiewicz

IPC: H01L29/76 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A stacked device is provided. The stacked device includes a plurality of dielectric support bridges on a substrate, and a first two-dimensional (2D) channel layer on each of the plurality of dielectric support bridges. The stacked device further includes a gate dielectric sheet on the first two-dimensional (2D) channel layer, and a second two-dimensional (2D) channel layer on the first two-dimensional (2D) channel layer. The stacked device further includes a second gate dielectric layer on the gate dielectric sheets.

公开(公告)号：US20240203904A1

公开(公告)日：2024-06-20

申请号：US18083994

申请日：2022-12-19

Applicant: International Business Machines Corporation

Inventor： FEE LI LIE ,  Hosadurga Shobha ,  Michael Rizzolo ,  Aakrati Jain ,  Sagarika Mukesh ,  Christopher J. Waskiewicz

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L23/5226

Abstract: A semiconductor structure is provided that includes a stress modulating pattern containing bonding dielectric layer. The stress modulating pattern containing bonding dielectric layer can be formed on a wafer, on a device-containing region that is present on a device wafer, or both a wafer and a device-containing region that is present on a device wafer. The stress modulating pattern is composed of a plurality of patterned structures (metal and/or dielectric) that are embedded at least partially within a bonding dielectric layer. Warpage modulation can be achieved using such a stress modulating pattern containing bonding dielectric layer.

公开(公告)号：US20230139379A1

公开(公告)日：2023-05-04

申请号：US17514545

申请日：2021-10-29

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Christopher J. Waskiewicz ,  Jay William Strane ,  Hemanth Jagannathan ,  Brent Anderson

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: VFET devices having a robust gate extension structure using late gate extension patterning and self-aligned gate and source/drain region contacts are provided. In one aspect, a VFET device includes: at least one bottom source/drain region present on a substrate; at least one fin disposed on the at least one bottom source/drain region, wherein the at least one fin serves as a vertical fin channel of the VFET device; a gate stack alongside the at least one fin; a gate extension metal adjacent to the gate stack at a base of the at least one fin; a barrier layer that separates the gate extension metal from the gate stack; and at least one top source/drain region at a top of the at least one fin. A VFET device that includes multiple VFETs present on a substrate, and a method of forming a VFET device are also provided.