公开(公告)号：US20190318970A1

公开(公告)日：2019-10-17

申请号：US16446808

申请日：2019-06-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Shogo Mochizuki ,  Chun Wing Yeung ,  Hemanth Jagannathan

IPC: H01L21/8238 ,  H01L21/768 ,  H01L29/45 ,  H01L29/167 ,  H01L29/161 ,  H01L29/06 ,  H01L29/08 ,  H01L23/535 ,  H01L27/092

Abstract: A method is presented for forming a transistor having reduced parasitic contact resistance. The method includes forming a first device over a semiconductor structure, forming a second device adjacent the first device, forming an ILD over the first and second devices, and forming recesses within the ILD to expose the source/drain regions of the first device and the source/drain regions of the second device. The method further includes forming a first dielectric layer over the ILD and the top surfaces of the source/drain regions of the first and second devices, a chemical interaction between the first dielectric layer and the source/drain regions of the second device resulting in second dielectric layers formed over the source/drain regions of the second device, and forming an epitaxial layer over the source/drain regions of the first device after removing remaining portions of the first dielectric layer.

公开(公告)号：US10431502B1

公开(公告)日：2019-10-01

申请号：US15954133

申请日：2018-04-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Shogo Mochizuki ,  Chun Wing Yeung ,  Hemanth Jagannathan

IPC: H01L21/70 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/167 ,  H01L29/45

Abstract: A method is presented for forming a transistor having reduced parasitic contact resistance. The method includes forming a first device over a semiconductor structure, forming a second device adjacent the first device, forming an ILD over the first and second devices, and forming recesses within the ILD to expose the source/drain regions of the first device and the source/drain regions of the second device. The method further includes forming a first dielectric layer over the ILD and the top surfaces of the source/drain regions of the first and second devices, a chemical interaction between the first dielectric layer and the source/drain regions of the second device resulting in second dielectric layers formed over the source/drain regions of the second device, and forming an epitaxial layer over the source/drain regions of the first device after removing remaining portions of the first dielectric layer.

公开(公告)号：US10388766B2

公开(公告)日：2019-08-20

申请号：US15791095

申请日：2017-10-23

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  Michael P. Belyansky ,  Choonghyun Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234

Abstract: A VFET device with a dual top spacer to prevent source/drain-to-gate short, and techniques for formation thereof are provided. In one aspect, a method of forming a VFET device includes: etching vertical fin channels in a substrate; forming a bottom source and drain in the substrate beneath the vertical fin channels; forming a bottom spacer on the bottom source and drain; depositing a gate dielectric and gate conductor onto the vertical fin channels; recessing the gate dielectric and gate conductor to expose tops of the vertical fin channels; selectively forming dielectric spacers on end portions of the gate dielectric and gate conductor adjacent to the tops of the vertical fin channels; depositing an encapsulation layer onto the vertical fin channels; recessing the encapsulation layer with the dielectric spacers serving as an etch stop; and forming top source and drains. A VFET device formed using the present techniques is also provided.

公开(公告)号：US20190237336A1

公开(公告)日：2019-08-01

申请号：US15883503

申请日：2018-01-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Junli Wang ,  Alexander Reznicek ,  Shogo Mochizuki ,  Joshua Rubin

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/51 ,  H01L21/3213

Abstract: A method of forming gate structures to a nanosheet device that includes forming at least two stacks of nanosheets, wherein each nanosheet includes a channel region portion having a gate dielectric layer present thereon. The method may further include forming a dual metal layer scheme on the gate dielectric layer of each nanosheet. The dual metal layer scheme including an etch stop layer of a first composition and a work function adjusting layer of a second composition, wherein the etch stop layer has a composition that provides that the work function adjusting layer is removable by a wet etch chemistry that is selective to the etch stop layer.

公开(公告)号：US20190229204A1

公开(公告)日：2019-07-25

申请号：US16369921

申请日：2019-03-29

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Shogo Mochizuki

IPC: H01L29/66 ,  H01L23/535 ,  H01L21/28 ,  H01L21/02 ,  H01L29/78 ,  H01L21/768 ,  H01L29/49 ,  H01L29/167 ,  H01L29/161 ,  H01L29/08 ,  H01L21/225

Abstract: A vertical transistor structure is provided that includes a bottom source/drain structure that includes a doped semiconductor buffer layer that contains a first dopant species having a first diffusion rate, and an epitaxial doped semiconductor layer that contains a second dopant species that has a second diffusion rate that is less than the first diffusion rate. During a junction anneal, the first dopant species readily diffuses from the doped semiconductor buffer layer into a pillar portion of a base semiconductor substrate to provide the bottom source/drain extension and bottom source/drain junction. No diffusion overrun is observed. During the junction anneal, the second dopant species remains in the epitaxial doped semiconductor layer providing a low resistance contact. The second dopant species does not interfere with the bottom source/drain extension and bottom source/drain junction due to limited diffusion of the second dopant species.

公开(公告)号：US20190181052A1

公开(公告)日：2019-06-13

申请号：US16266469

申请日：2019-02-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  ChoongHyun Lee ,  Shogo Mochizuki

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a silicon (Si) channel for a first device, forming a first interfacial layer over the Si channel, forming a silicon-germanium (SiGe) channel for a second device, forming a second interfacial layer over the SiGe channel, and selectively removing germanium oxide (GeOx) from the second interfacial layer by applying a combination of hydrogen (H2) and hydrogen chloride (HCl). The second interfacial is silicon germanium oxide (SiGeOx) and removal of the GeOx results in formation of a pure silicon dioxide (SiO2) layer.

公开(公告)号：US20190181012A1

公开(公告)日：2019-06-13

申请号：US16265784

申请日：2019-02-01

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/285 ,  H01L29/66 ,  H01L29/24 ,  H01L21/768 ,  H01L29/08 ,  H01L29/78 ,  H01L29/267

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

公开(公告)号：US10290747B2

公开(公告)日：2019-05-14

申请号：US16011445

申请日：2018-06-18

Applicant: International Business Machines Corporation

Inventor： Keith E. Fogel ,  Pouya Hashemi ,  Shogo Mochizuki ,  Alexander Reznicek

IPC: H01L29/94 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/06

Abstract: MIS capacitors are formed using a finned semiconductor structure. A highly doped region including the fins is formed within the structure and forms one plate of a MIS capacitor. A metal layer forms a second capacitor plate that is separated from the first plate by a high-k capacitor dielectric layer formed directly on the highly doped fins. Contacts are electrically connected to the capacitor plates. A highly doped implantation layer having a conductivity type opposite to that of the highly doped region provides electrical isolation within the structure.

公开(公告)号：US20190115479A1

公开(公告)日：2019-04-18

申请号：US15783029

申请日：2017-10-13

Applicant: International Business Machines Corporation

Inventor： Chun Wing Yeung ,  Choonghyun Lee ,  Shogo Mochizuki ,  Ruqiang Bao

IPC: H01L29/808 ,  H01L29/22 ,  H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423

Abstract: Techniques for integrating a self-aligned heterojunction for TFETs in a vertical GAA architecture are provided. In one aspect, a method of forming a vertical TFET device includes: forming a doped SiGe layer on a Si substrate; forming fins that extend through the doped SiGe layer and partway into the Si substrate such that each of the fins includes a doped SiGe portion disposed on a Si portion with a heterojunction therebetween, wherein the SiGe portion is a source and the Si portion is a channel; selectively forming oxide spacers, aligned with the heterojunction, along opposite sidewalls of only the doped SiGe portion; and forming a gate stack around the Si portion and doped SiGe that is self-aligned with the heterojunction. A vertical TFET device formed by the method is also provided.

公开(公告)号：US10262904B2

公开(公告)日：2019-04-16

申请号：US15811164

申请日：2017-11-13

Applicant: International Business Machines Corporation

Inventor： Oleg Gluschenkov ,  Sanjay C. Mehta ,  Shogo Mochizuki ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/167 ,  H01L29/161 ,  H01L21/761 ,  H01L29/08 ,  H01L29/78 ,  H01L27/088

Abstract: An nFET vertical transistor is provided in which a p-doped top source/drain structure is formed in contact with an n-doped semiconductor region that is present on a topmost surface of a vertical nFET channel. The p-doped top source/drain structure is formed utilizing a low temperature (550° C. or less) epitaxial growth process.