公开(公告)号：US12094793B2

公开(公告)日：2024-09-17

申请号：US18380276

申请日：2023-10-16

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Chii Shang Hong ,  Teck Sim Lee ,  Bernd Schmoelzer ,  Ke Yan Tean ,  Lee Shuang Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L23/3121 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49506 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49838 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L23/49503 ,  H01L23/49575 ,  H01L2924/181

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

公开(公告)号：US11929298B2

公开(公告)日：2024-03-12

申请号：US17097098

申请日：2020-11-13

Applicant: Infineon Technologies AG

Inventor： Jo Ean Joanna Chye ,  Edward Fuergut ,  Ralf Otremba

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/31 ,  H01L23/46 ,  H01L23/495

CPC classification number: H01L23/367 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/46 ,  H01L23/49568

Abstract: A molded semiconductor package includes: a semiconductor die embedded in a mold compound; a first heat spreader partly embedded in the mold compound and thermally coupled to a first side of the semiconductor die; and a second heat spreader partly embedded in the mold compound and thermally coupled to a second side of the semiconductor die opposite the first side. The first heat spreader includes at least one heat dissipative structure protruding from a side of the first heat spreader uncovered by the mold compound and facing away from the semiconductor die. The mold compound is configured to channel a fluid over the at least one heat dissipative structure in a direction parallel to the first side of the power semiconductor die. Corresponding methods of production and electronic assemblies are also described.

公开(公告)号：US20230035550A1

公开(公告)日：2023-02-02

申请号：US17873909

申请日：2022-07-26

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann ,  Edward Fuergut ,  Uwe Schindler

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/367 ,  H01L23/31

Abstract: A semiconductor device module includes an application board, a plurality of semiconductor device packages disposed on the application board, each one of the semiconductor device packages including a semiconductor die, a leadframe including a plurality of leads, the leads including a spring support and a heat dissipation element, and an encapsulant embedding the semiconductor die and first portions of the leads, an external heatsink, and one or more thermally conductive interface layers disposed between the semiconductor device package and the heatsink.

公开(公告)号：US20220285283A1

公开(公告)日：2022-09-08

申请号：US17752224

申请日：2022-05-24

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ravi Keshav Joshi ,  Ralf Siemieniec ,  Thomas Basler ,  Martin Gruber ,  Jochen Hilsenbeck ,  Dethard Peters ,  Roland Rupp ,  Wolfgang Scholz

IPC: H01L23/532 ,  H01L29/16 ,  H01L21/768 ,  H01L23/00 ,  H01L29/45

Abstract: A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.

公开(公告)号：US11040872B2

公开(公告)日：2021-06-22

申请号：US16595532

申请日：2019-10-08

Applicant: Infineon Technologies AG

Inventor： Claus Waechter ,  Edward Fuergut ,  Bernd Goller ,  Michael Ledutke ,  Dominic Maier

IPC: H01L27/14 ,  B81C1/00 ,  B81B7/00

Abstract: The method comprises fabricating a semiconductor panel comprising a plurality of semiconductor devices, fabricating a cap panel comprising a plurality of caps, bonding the cap panel onto the semiconductor panel so that each one of the caps covers one or more of the semiconductor devices, and singulating the bonded panels into a plurality of semiconductor modules.

公开(公告)号：US20210043555A1

公开(公告)日：2021-02-11

申请号：US16944303

申请日：2020-07-31

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Thomas Basler ,  Reinhold Bayerer ,  Ivan Nikitin

IPC: H01L23/498 ,  H01L23/66 ,  H01L23/29 ,  H01L21/56 ,  H01L21/48

Abstract: An electronic device and method is disclosed. In one example, the electronic device includes an electrically insulating material, a first load electrode arranged on a first surface of the electrically insulating material, and a second load electrode arranged on a second surface of the electrically insulating material opposite to the first surface, wherein the load electrodes are separated by the electrically insulating material along the entire length on which the load electrodes have opposite sections, wherein surfaces of the load electrodes facing away from the electrically insulating material are uncovered by the electrically insulating material.

公开(公告)号：US10347554B2

公开(公告)日：2019-07-09

申请号：US15462858

申请日：2017-03-19

Applicant: Infineon Technologies AG

Inventor： Norbert Joson Santos ,  Edward Fuergut ,  Sanjay Kumar Murugan

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/40 ,  H01L23/367 ,  H01L23/495 ,  H01L21/56 ,  H01L21/02 ,  H01L21/67 ,  H01L33/48 ,  H01L33/54 ,  H01L33/62 ,  H01L33/64 ,  H01L21/3105 ,  H01L33/58 ,  H01L33/60 ,  H01L43/02 ,  H01L23/24

Abstract: An electronic component which comprises an electrically conductive carrier, an electronic chip on the carrier, an encapsulant encapsulating at least part of at least one of the carrier and the electronic chip, and a functional structure covering a surface portion of the encapsulant, wherein at least part of the covered surface portion of the encapsulant is spatially selectively roughened.

公开(公告)号：US20190157190A1

公开(公告)日：2019-05-23

申请号：US15816090

申请日：2017-11-17

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Martin Gruber

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor device package includes a lead frame, a first power semiconductor device mounted on a first part of the lead frame and a second power semiconductor device mounted on a second part of the lead frame. The first power semiconductor device is encapsulated by a first mold compound. The second power semiconductor device is encapsulated by a second mold compound. The first mold compound and the second mold compound are substantially separate from each other. The lead frame includes an intermediate part arranged between the first part and the second part. The intermediate part is not covered by the first mold compound or by the second mold compound.

公开(公告)号：US10125012B2

公开(公告)日：2018-11-13

申请号：US14011621

申请日：2013-08-27

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Horst Theuss

IPC: B81B7/00 ,  B81C1/00

Abstract: A MEMS device includes a first chip and a MEMS chip. The first chip has a mounting surface and includes at least an integrated circuit. The MEMS chip has a main surface on which a first set of contact pads for contacting the MEMS device and a second set of contact pads for contacting the first chip are arranged. The first chip is mechanically attached and electrically connected to the second set of contact pads via the mounting surface facing the main surface. The mounting surface of the first chip is at least 25% smaller than the main surface of the MEMS chip.

公开(公告)号：US10121690B2

公开(公告)日：2018-11-06

申请号：US14757589

申请日：2015-12-23

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Edward Fuergut ,  Joachim Mahler

IPC: H01L21/00 ,  H01L21/683 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: Various embodiments provide method of manufacturing a semiconductor component, wherein the method comprises providing a layer stack comprising a carrier and a thinned wafer comprising a metallization layer on one side, wherein the thinned wafer is placed on a first side of the carrier; forming an encapsulation encapsulating the layer stack at least partially; and subsequently thinning the carrier from a second side of the carrier, wherein the second side is opposite to the first side of the carrier.