公开(公告)号：US20180331204A1

公开(公告)日：2018-11-15

申请号：US15979050

申请日：2018-05-14

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Romain Esteve ,  Daniel Kueck ,  Dethard Peters ,  Ralf Siemieniec ,  Bernd Zippelius

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L21/66 ,  G06F17/50 ,  H01L27/02

Abstract: By using at least one of a processor device and model transistor cells, a set of design parameters for at least one of a transistor cell and a drift structure of a wide band-gap semiconductor device is determined, wherein an on state failure-in-time rate and an off state failure-in-time rate of a gate dielectric of the transistor cell are within a same order of magnitude for a predefined on-state gate-to-source voltage, a predefined off-state gate-to-source voltage, and a predefined off-state drain-to-source voltage.

公开(公告)号：US20180308938A1

公开(公告)日：2018-10-25

申请号：US15959661

申请日：2018-04-23

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Romain Esteve ,  Daniel Kueck

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a trench extending from a first surface into a SiC semiconductor body. The trench has a first sidewall, a second sidewall opposite to the first sidewall, and a trench bottom. A gate electrode is arranged in the trench and is electrically insulated from the SiC semiconductor body by a trench dielectric. A body region of a first conductivity type adjoins the first sidewall. A shielding structure of the first conductivity type adjoins at least a portion of the second sidewall and the trench bottom. A first section of the trench bottom and a second section of the trench bottom are offset to one another by a vertical offset along a vertical direction extending from the first surface to a second surface of the SiC semiconductor body opposite to the first surface.

公开(公告)号：US10074741B2

公开(公告)日：2018-09-11

申请号：US15057704

申请日：2016-03-01

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Romain Esteve ,  Dethard Peters ,  Roland Rupp ,  Ralf Siemieniec

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/66 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L27/06 ,  H01L29/872 ,  H01L29/36 ,  H01L29/861 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L29/7804 ,  H01L27/0629 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/401 ,  H01L29/417 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: A semiconductor device includes trench structures that extend from a first surface into a semiconductor body. The trench structures include a gate structure and a contact structure that extends through the gate structure, respectively. Transistor mesas are between the trench structures. Each transistor mesa includes a body zone forming a first pn junction with a drift structure and a second pn junction with a source zone. Diode regions directly adjoin one of the contact structures form a third pn junction with the drift structure, respectively.

公开(公告)号：US20180248000A1

公开(公告)日：2018-08-30

申请号：US15957765

申请日：2018-04-19

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L21/04 ,  H01L29/10

CPC classification number: H01L29/063 ,  H01L21/02236 ,  H01L21/045 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: A vertical transistor device includes a silicon-carbide substrate, a gate trench formed in the silicon-carbide substrate, a body region adjacent the gate trench, a source region adjacent the gate trench and above the body region, and a dielectric material covering a bottom and a sidewall of the gate trench. A thickness of the dielectric material is greater at the bottom of the gate trench than along the sidewall of the gate trench. Further vertical transistor device embodiments and corresponding methods of manufacture are also described.

公开(公告)号：US09577073B2

公开(公告)日：2017-02-21

申请号：US14567504

申请日：2014-12-11

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/423 ,  H01L21/324 ,  H01L21/04 ,  H01L21/02 ,  H01L21/311 ,  H01L29/16

CPC classification number: H01L29/063 ,  H01L21/02236 ,  H01L21/045 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed.

Abstract translation: 一种碳化硅半导体衬底，其具有多个第一掺杂区域，该第一掺杂区域在主表面之间彼此横向间隔开，并且形成从主表面延伸至位于第一掺杂区域之上的第三掺杂区域的第二掺杂区域 。 形成从主表面延伸到第一掺杂区的第四掺杂区。 形成具有布置在一个第一掺杂区域的一部分上的底部的栅极沟槽。 将高温步骤施加到衬底上，以便沿着沟槽的侧壁重新排列碳化硅原子，并在栅极沟槽中形成圆角。 去除在离开衬底的高温步骤期间沿着栅极沟槽的侧壁形成的表面层。

公开(公告)号：US09530850B2

公开(公告)日：2016-12-27

申请号：US14976566

申请日：2015-12-21

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner

IPC: H01L29/423 ,  H01L29/739 ,  H01L29/16 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/4236 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/049 ,  H01L21/823462 ,  H01L24/48 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7813 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/45099

Abstract: A semiconductor device includes a transistor cell with a stripe-shaped trench gate structure that extends from a first surface into a semiconductor body. A gate connector structure at a distance to the first surface is electrically connected to a gate electrode in the trench gate structure. A gate dielectric separates the gate electrode from the semiconductor body. First sections of the gate dielectric outside a vertical projection of the gate connector structure are thinner than second sections within the vertical projection of the gate connector structure.

Abstract translation: 半导体器件包括具有从第一表面延伸到半导体本体的条形沟槽栅极结构的晶体管单元。 距离第一表面一定距离的栅极连接器结构电连接到沟槽栅极结构中的栅电极。 栅极电介质将栅电极与半导体本体分开。 栅极连接器结构的垂直投影外部的栅极电介质的第一部分比栅极连接器结构的垂直投影内的第​​二部分薄。

公开(公告)号：US20160260829A1

公开(公告)日：2016-09-08

申请号：US15057704

申请日：2016-03-01

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Romain Esteve ,  Dethard Peters ,  Roland Rupp ,  Ralf Siemieniec

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/04 ,  H01L29/417

CPC classification number: H01L29/7804 ,  H01L27/0629 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/401 ,  H01L29/417 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: A semiconductor device includes trench structures that extend from a first surface into a semiconductor body. The trench structures include a gate structure and a contact structure that extends through the gate structure, respectively. Transistor mesas are between the trench structures. Each transistor mesa includes a body zone forming a first pn junction with a drift structure and a second pn junction with a source zone. Diode regions directly adjoin one of the contact structures form a third pn junction with the drift structure, respectively.

Abstract translation: 半导体器件包括从第一表面延伸到半导体本体的沟槽结构。 沟槽结构包括分别延伸穿过栅极结构的栅极结构和接触结构。 晶体管台面位于沟槽结构之间。 每个晶体管台面包括形成具有漂移结构的第一pn结的主体区和与源区的第二pn结。 与接触结构中的一个直接邻接的二极管区域分别与漂移结构形成第三pn结。

公开(公告)号：US20250107202A1

公开(公告)日：2025-03-27

申请号：US18882226

申请日：2024-09-11

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Hans Weber ,  Michael Hell ,  Wolfgang Bergner ,  Armin Tilke ,  Grazvydas Ziemys ,  Alexey Mikhaylov ,  Gerald Rescher

IPC: H01L29/40 ,  H01L29/16 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

Abstract: A transistor device is disclosed. The transistor device includes a semiconductor body and plurality of transistor cells. Each transistor cell includes: a drift region and a source region of a first doping type; a body region of a second doping type complementary to the first doping type; a field shaping region of the second doping type connected to a source node; and a gate electrode connected to a gate node. The gate electrode is arranged in a trench extending from a first surface into the semiconductor body. The gate electrode is dielectrically insulated from the body region by a gate dielectric. At least portions of the gate electrode are dielectrically insulated from the drift region by a field dielectric. The field shaping region adjoins the trench. The field dielectric comprises a high-k dielectric.

公开(公告)号：US11791383B2

公开(公告)日：2023-10-17

申请号：US17387504

申请日：2021-07-28

Applicant: Infineon Technologies AG

Inventor： Saurabh Roy ,  Thomas Aichinger ,  Hans-Joachim Schulze

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L29/51

CPC classification number: H01L29/1608 ,  H01L29/516 ,  H01L29/66053 ,  H01L29/78391

Abstract: A semiconductor device includes a SiC substrate and a plurality of transistor cells formed in the SiC substrate and electrically connected in parallel to form a transistor. Each transistor cell includes a gate structure including a gate electrode and a gate dielectric stack separating the gate electrode from the SiC substrate. The gate dielectric stack includes a ferroelectric insulator. The transistor has a specified operating temperature range, and the ferroelectric insulator is doped with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor. A corresponding method of producing the semiconductor device is also described.

公开(公告)号：US11626477B2

公开(公告)日：2023-04-11

申请号：US17375034

申请日：2021-07-14

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Thomas Basler ,  Wolfgang Bergner ,  Rudolf Elpelt ,  Romain Esteve ,  Michael Hell ,  Daniel Kueck ,  Caspar Leendertz ,  Dethard Peters ,  Hans-Joachim Schulze

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.