公开(公告)号：US10146711B2

公开(公告)日：2018-12-04

申请号：US15196014

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit S. Bains ,  George Vergis ,  Christopher E. Cox ,  James A. McCall ,  Chong J. Zhao ,  Suneeta Sah ,  Pete D. Vogt ,  John R. Goles

IPC: G06F13/16 ,  G11C14/00 ,  G11C11/4096 ,  G06F13/40

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US09786353B2

公开(公告)日：2017-10-10

申请号：US15047427

申请日：2016-02-18

Applicant: Intel Corporation

Inventor： Mozhgan Mansuri ,  Aaron Martin ,  James A. McCall

IPC: G11C7/00 ,  G11C11/4076 ,  H03K5/14 ,  G11C7/22 ,  G11C7/10 ,  G06F1/10 ,  H04L7/033 ,  H03K5/00

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/4234 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4093 ,  H03K5/14 ,  H03K2005/00052 ,  H04L7/0337

Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.

公开(公告)号：US20170140809A1

公开(公告)日：2017-05-18

申请号：US15351195

申请日：2016-11-14

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Randy B. Osborne ,  Michael Gutzmann ,  James A. McCall

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G06F13/1684 ,  G06F13/1689 ,  G11C11/4076 ,  G11C11/4096

Abstract: Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory with multiple ranks. Other embodiments are also disclosed and claimed.

公开(公告)号：US09152257B2

公开(公告)日：2015-10-06

申请号：US13730642

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： James A. McCall ,  Kuljit S. Bains ,  Derek M. Conrow ,  Aaron Martin

IPC: H03K3/012 ,  G06F3/041 ,  H03K19/00 ,  H03K19/0175

CPC classification number: H03K19/0008 ,  G06F3/041 ,  G06F3/0412 ,  H03K19/0005 ,  H03K19/017509 ,  H03K19/017545

Abstract: An output driver includes control logic configured to switch on a pull-up circuit and a pull-down circuit to provide an output impedance for a logic low on a transmission line. The output driver includes a variable pull-up resistor. The control logic is configured to switch on the pull-up circuit to a first value of impedance to drive a logic high on the transmission line. The control logic is configured to switch on the pull-up circuit to a second value of impedance and to switch on the pull-down circuit to provide the output impedance to drive a logic low on the transmission line. The system could alternatively be configured for the inverse to switch on a combination of pull-up and pull-down circuits for a logic high, where the pull-down circuit is switched on for a logic low.

Abstract translation: 输出驱动器包括被配置为接通上拉电路和下拉电路以提供传输线路上的逻辑低电平的输出阻抗的控制逻辑。 输出驱动器包括一个可变上拉电阻。 控制逻辑被配置为将上拉电路接通到第一阻抗值，以驱动传输线上的逻辑高电平。 控制逻辑被配置为将上拉电路接通到第二阻抗值，并且接通下拉电路以提供输出阻抗以驱动传输线上的逻辑低电平。 可替代地，该系统可以被配置为用于将逻辑高的上拉电路和下拉电路的组合打开，其中下拉电路被接通为逻辑低电平。