公开(公告)号：US08901677B2

公开(公告)日：2014-12-02

申请号：US14198480

申请日：2014-03-05

Applicant: Intermolecular, Inc.

Inventor： Frank Greer ,  Edwin Adhiprakasha ,  Chi-I Lang ,  Ratsamee Limdulpaiboon ,  Sandip Niyogi ,  Kurt Pang ,  J. Watanabe

IPC: H01L21/336 ,  H01L21/311 ,  H01L29/02

CPC classification number: H01L21/31122 ,  H01L21/02052 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02301 ,  H01L21/02304 ,  H01L21/02312 ,  H01L21/02315 ,  H01L21/28255 ,  H01L29/02

Abstract: A germanium-containing semiconductor surface is prepared for formation of a dielectric overlayer (e.g., a thin layer of high-k gate dielectric) by (1) removal of native oxide, for example by wet cleaning, (2) additional cleaning with hydrogen species, (3) in-situ formation of a controlled monolayer of GeO2, and (4) in-situ deposition of the dielectric overlayer to prevent uncontrolled regrowth of native oxide. The monolayer of GeO2 promotes uniform nucleation of the dielectric overlayer, but it too thin to appreciably impact the effective oxide thickness of the dielectric overlayer.

Abstract translation: 制备含锗的半导体表面，用于通过（1）去除天然氧化物，例如通过湿法清洁来形成电介质覆盖层（例如，高k栅极电介质的薄层），（2）用氢物质进行额外的清洁 ，（3）原位形成受控单层的GeO 2，以及（4）电介质覆层的原位沉积，以防止天然氧化物的不受控制的再生长。 GeO2的单层促进电介质覆盖层的均匀成核，但它太薄而不能明显影响电介质覆盖层的有效氧化物厚度。

公开(公告)号：US08871860B2

公开(公告)日：2014-10-28

申请号：US13971613

申请日：2013-08-20

Applicant: Intermolecular, Inc.

Inventor： Anh Duong ,  Tony Chiang ,  Zachary M. Fresco ,  Nitin Kumar ,  Chi-I Lang ,  Jinhong Tong ,  Anna Tsizelmon

IPC: H01L21/02 ,  H01L21/768 ,  C09D129/04 ,  H01L21/3105

CPC classification number: H01L23/5329 ,  C09D129/04 ,  H01L21/02063 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of modifying a patterned semiconductor substrate are presented including: providing a patterned semiconductor substrate surface including a dielectric region and a conductive region; and applying an amphiphilic surface modifier to the dielectric region to modify the dielectric region. In some embodiments, modifying the dielectric region includes modifying a wetting angle of the dielectric region. In some embodiments, modifying the wetting angle includes making a surface of the dielectric region hydrophilic. In some embodiments, methods further include applying an aqueous solution to the patterned semiconductor substrate surface. In some embodiments, the conductive region is selectively enhanced by the aqueous solution. In some embodiments, methods further include providing the dielectric region formed of a low-k dielectric material. In some embodiments, applying the amphiphilic surface modifier modifies an interaction of the low-k dielectric region with a subsequent process.

Abstract translation: 提出了修改图案化半导体衬底的方法，包括：提供包括电介质区域和导电区域的图案化半导体衬底表面; 以及将两亲表面改性剂施加到所述电介质区域以改变所述电介质区域。 在一些实施例中，修改电介质区域包括改变电介质区域的润湿角度。 在一些实施例中，改变润湿角度包括使介电区域的表面成为亲水性。 在一些实施方案中，方法还包括将水溶液施加到图案化的半导体衬底表面。 在一些实施例中，导电区域被水溶液选择性地增强。 在一些实施例中，方法还包括提供由低k电介质材料形成的电介质区域。 在一些实施方案中，施加两亲表面改性剂修饰低k电介质区域与随后工艺的相互作用。

公开(公告)号：US08821985B2

公开(公告)日：2014-09-02

申请号：US13667986

申请日：2012-11-02

Applicant: Intermolecular, Inc.

Inventor： ShouQian Shao ,  Chi-I Lang ,  Sandip Niyogi ,  Jinhong Tong

IPC: B05D3/00 ,  H05H1/00

CPC classification number: C23C16/45542 ,  B01J19/0046 ,  B01J2219/0043 ,  B01J2219/00443 ,  B01J2219/00635 ,  B01J2219/00754 ,  B01J2219/00756 ,  C23C16/04 ,  C23C16/45565

Abstract: Methods and apparatuses for combinatorial processing are disclosed. Methods include introducing a substrate into a processing chamber. Methods further include forming a first film on a surface of a first site-isolated region on the substrate and forming a second film on a surface of a second site-isolated region on the substrate. The methods further include exposing the first film to a plasma having a first source gas to form a first treated film on the substrate and exposing the second film to a plasma having a second source gas to form a second treated film on the substrate without etching the first treated film in the processing chamber. In addition, methods include evaluating results of the treated films post processing.

Abstract translation: 公开了用于组合处理的方法和装置。 方法包括将衬底引入处理室。 方法还包括在衬底上的第一位点隔离区域的表面上形成第一膜，并在衬底上的第二位置隔离区域的表面上形成第二膜。 所述方法还包括将第一膜暴露于具有第一源气体的等离子体，以在衬底上形成第一处理膜，并将第二膜暴露于具有第二源气体的等离子体，以在衬底上形成第二处理膜，而不蚀刻 处理室中的第一处理膜。 此外，方法包括评估经处理的膜后处理的结果。

公开(公告)号：US20140174911A1

公开(公告)日：2014-06-26

申请号：US13725846

申请日：2012-12-21

Applicant: INTERMOLECULAR, INC.

Inventor： Chi-I Lang

IPC: C23C14/35 ,  H01L21/02

CPC classification number: H01L21/0226 ,  C22C27/02 ,  C23C14/3414 ,  H01J37/34 ,  H01J37/3426

Abstract: Embodiments provided herein describe methods and systems for depositing material onto a surface. A target including a material in a porous state is provided. The density of the material in the porous state is less than 89% of the absolute density of the material. The target is positioned over a surface. At least some of the material is caused to be ejected from the target and deposited onto the surface.

Abstract translation: 本文提供的实施例描述了将材料沉积到表面上的方法和系统。 提供了包括多孔状态的材料的靶。 多孔态的材料的密度小于材料的绝对密度的89％。 目标位于表面上方。 使至少一些材料从靶上喷出并沉积在表面上。

公开(公告)号：US20140174907A1

公开(公告)日：2014-06-26

申请号：US13725133

申请日：2012-12-21

Applicant: INTERMOLECULAR, INC.

Inventor： Hong Sheng Yang ,  Kent Riley Child ,  Chi-I Lang ,  James Tsung

IPC: C23C14/34

CPC classification number: C23C14/04 ,  B01J19/0046 ,  B01J2219/0043 ,  B01J2219/00527 ,  B01J2219/00596 ,  B01J2219/00754 ,  B01J2219/00756 ,  C23C14/351 ,  C23C14/352 ,  H01J37/34

Abstract: A deposition chamber is provided. The deposition chamber includes a plurality of sputter guns disposed within the chamber, wherein the plurality of sputter guns are operable to vertically extend and retract within the chamber and wherein each gun of the plurality of sputter guns is pivotable around a pivot axis. The chamber includes a substrate support rotatable around a first axis and a second axis and a plate disposed over the substrate support. The plate has a plurality of apertures extending therethrough. The plurality of apertures includes an aperture located below each sputter gun of the plurality of sputter guns and a centrally located aperture.

Abstract translation: 提供沉积室。 沉积室包括设置在室内的多个溅射枪，其中多个溅射枪可操作以在室内垂直延伸和缩回，并且其中多个溅射枪中的每个喷枪可围绕枢转轴线枢转。 腔室包括可围绕第一轴线旋转的基底支撑件和第二轴线以及设置在基板支撑件上方的板材。 该板具有延伸穿过其中的多个孔。 多个孔包括位于多个溅射枪的每个溅射枪下方的孔和位于中心的孔。

公开(公告)号：US20140127422A1

公开(公告)日：2014-05-08

申请号：US13667986

申请日：2012-11-02

Applicant: INTERMOLECULAR, INC.

Inventor： ShouQian Shao ,  Chi-I Lang ,  Sandip Niyogi ,  Jinhong Tong

IPC: B05D3/10

CPC classification number: C23C16/45542 ,  B01J19/0046 ,  B01J2219/0043 ,  B01J2219/00443 ,  B01J2219/00635 ,  B01J2219/00754 ,  B01J2219/00756 ,  C23C16/04 ,  C23C16/45565

Abstract: Methods and apparatuses for combinatorial processing are disclosed. Methods include introducing a substrate into a processing chamber. Methods further include forming a first film on a surface of a first site-isolated region on the substrate and forming a second film on a surface of a second site-isolated region on the substrate. The methods further include exposing the first film to a plasma having a first source gas to form a first treated film on the substrate and exposing the second film to a plasma having a second source gas to form a second treated film on the substrate without etching the first treated film in the processing chamber. In addition, methods include evaluating results of the treated films post processing.

Abstract translation: 公开了用于组合处理的方法和装置。 方法包括将衬底引入处理室。 方法还包括在衬底上的第一位点隔离区域的表面上形成第一膜，并在衬底上的第二位置隔离区域的表面上形成第二膜。 所述方法还包括将第一膜暴露于具有第一源气体的等离子体，以在衬底上形成第一处理膜，并将第二膜暴露于具有第二源气体的等离子体，以在衬底上形成第二处理膜，而不蚀刻 处理室中的第一处理膜。 此外，方法包括评估经处理的膜后处理的结果。

公开(公告)号：US20140014892A1

公开(公告)日：2014-01-16

申请号：US14028281

申请日：2013-09-16

Applicant: Intermolecular, Inc.

Inventor： Tony P. Chiang ,  Chi-I Lang ,  Prashant B. Phatak

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/148 ,  H01L45/149 ,  H01L45/1616 ,  H01L45/1641

Abstract: A resistive-switching memory element is described. The memory element includes a first electrode, a porous layer over the first electrode including a point defect embedded in a plurality of pores of the porous layer, and a second electrode over the porous layer, wherein the nonvolatile memory element is configured to switch between a high resistive state and a low resistive state.

Abstract translation: 描述电阻式切换存储元件。 所述存储元件包括第一电极，所述第一电极上的多孔层，包括嵌入所述多孔层的多个孔中的点缺陷，以及位于所述多孔层上的第二电极，其中所述非易失性存储元件构造成在 高电阻状态和低电阻状态。

公开(公告)号：US20130334491A1

公开(公告)日：2013-12-19

申请号：US13972515

申请日：2013-08-21

Applicant: Intermolecular Inc.

Inventor： Zhi-Wen Wen Sun ,  Tony P. Chiang ,  Chi-I Lang ,  Jinhong Tong

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616

Abstract: Methods for forming a NiO film on a substrate for use with a resistive switching memory device are presenting including: preparing a nickel ion solution; receiving the substrate, where the substrate includes a bottom electrode, the bottom electrode utilized as a cathode; forming a Ni(OH)2 film on the substrate, where the forming the Ni(OH)2 occurs at the cathode; and annealing the Ni(OH)2 film to form the NiO film, where the NiO film forms a portion of a resistive switching memory element. In some embodiments, methods further include forming a top electrode on the NiO film and before the forming the Ni(OH)2 film, pre-treating the substrate. In some embodiments, methods are presented where the bottom electrode and the top electrode are a conductive material such as: Ni, Pt, Ir, Ti, Al, Cu, Co, Ru, Rh, a Ni alloy, a Pt alloy, an Ir alloy, a Ti alloy, an Al alloy, a Cu alloy, a Co alloy, a Ru alloy, and an Rh alloy.

Abstract translation: 在电阻式切换存储装置使用的基板上形成NiO膜的方法包括：制备镍离子溶液; 接收衬底，其中衬底包括底部电极，用作阴极的底部电极; 在衬底上形成Ni（OH）2膜，其中在阴极处形成Ni（OH）2; 并且还原Ni（OH）2膜以形成NiO膜，其中NiO膜形成电阻式开关存储元件的一部分。 在一些实施例中，方法还包括在NiO膜上形成顶部电极，并且在形成Ni（OH）2膜之前，预处理衬底。 在一些实施例中，呈现了底部电极和顶部电极为导电材料的方法，例如：Ni，Pt，Ir，Ti，Al，Cu，Co，Ru，Rh，Ni合金，Pt合金，Ir 合金，Ti合金，Al合金，Cu合金，Co合金，Ru合金和Rh合金。

公开(公告)号：US20130260508A1

公开(公告)日：2013-10-03

申请号：US13909324

申请日：2013-06-04

Applicant: Intermolecular Inc.

Inventor： Nitin Kumar ,  Tony P. Chiang ,  Chi-I Lang ,  Zhi-Wen Wen Sun ,  Jinhong Tong

IPC: H01L45/00

CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

公开(公告)号：US08865518B2

公开(公告)日：2014-10-21

申请号：US13909324

申请日：2013-06-04

Applicant: Intermolecular Inc.

Inventor： Nitin Kumar ,  Tony P. Chiang ,  Chi-I Lang ,  Zhi-Wen Wen Sun ,  Jihong Tong

IPC: H01L21/00

CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.