公开(公告)号：US20100090780A1

公开(公告)日：2010-04-15

申请号：US12588432

申请日：2009-10-15

Applicant: In Sang Song ,  Chul Soon Park ,  Dong Yun Jung ,  Ki Chan Eun ,  Jae Jin Lee ,  Seong Jun Cho

Inventor： In Sang Song ,  Chul Soon Park ,  Dong Yun Jung ,  Ki Chan Eun ,  Jae Jin Lee ,  Seong Jun Cho

IPC: H01P1/18

CPC classification number: H01P1/184

Abstract: A phase shifter includes a substrate; a signal line formed on a specific region in an upper surface of the substrate; and an air gap which is formed within the substrate and changes effective permittivity of the substrate to delay phase of a signal supplied to the signal line. The phase shifter delays a phase of a signal by controlling effective permittivity using an air gap, thereby having outstandingly low insertion loss as compared to existing phase shifters. Further, the phase shifter can be manufactured in a same length as a reference line so that the phase shifter can be in a compact size.

Abstract translation: 移相器包括基板; 形成在所述基板的上表面的特定区域上的信号线; 以及形成在衬底内的气隙，并且改变衬底的有效介电常数以延迟提供给信号线的信号的相位。 移相器通过使用气隙控制有效介电常数来延迟信号的相位，从而与现有的移相器相比具有非常低的插入损耗。 此外，移相器可以制造成与参考线相同的长度，使得移相器可以是紧凑的尺寸。

公开(公告)号：US07646318B2

公开(公告)日：2010-01-12

申请号：US12181769

申请日：2008-07-29

Applicant: Jae Jin Lee ,  Jun Young Lee ,  Moo Kyoung Chung ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Jae Jin Lee ,  Jun Young Lee ,  Moo Kyoung Chung ,  Seong Mo Park ,  Nak Woong Eum

IPC: H03M7/00

CPC classification number: H04N19/42 ,  H04N19/44 ,  H04N19/91

Abstract: Provided is an H.264 Context Adaptive Variable Length Coding (CAVLC) decoding method based on an Application-Specific Instruction-set Processor (ASIP). The H.264 CAVLC decoding method includes determining a plurality of comparison bit strings on the basis of a table of a decoding coefficient, storing lengths of the comparison bit strings in a first register, storing code values of the comparison bit strings in a second register, comparing an input bit stream with the comparison bit strings based on the lengths and code values of the comparison bit strings, and determining value of the decoding coefficient according to a result of comparison between the input bit stream and the comparison bit strings. The method extracts a decoding coefficient using a register in an ASIP without accessing a memory and prevents a reduction in speed caused by memory access, thereby increasing the decoding speed of an H.264 decoder.

Abstract translation: 提供了一种基于应用特定指令集处理器（ASIP）的H.264上下文自适应可变长度编码（CAVLC）解码方法。 H.264 CAVLC解码方法包括：基于解码系数的表确定多个比较比特串，将比较比特列的长度存储在第一寄存器中，将比较比特列的代码值存储在第二寄存器 根据比较比特串的长度和码值比较输入比特流与比较比特串，并根据输入比特流和比较比特串之间的比较结果确定解码系数的值。 该方法使用ASIP中的寄存器提取解码系数，而不访问存储器，并且防止由存储器访问引起的速度降低，从而提高H.264解码器的解码速度。

公开(公告)号：US07126411B2

公开(公告)日：2006-10-24

申请号：US10999593

申请日：2004-11-30

Applicant: Ji Eun Jang ,  Jae Jin Lee

Inventor： Ji Eun Jang ,  Jae Jin Lee

IPC: G05F1/10

CPC classification number: H03K17/302 ,  G11C5/145 ,  H02M3/07

Abstract: Disclosed is a high voltage generator comprising: a first voltage level detector for detecting a voltage level of the high voltage; a second voltage level detector for detecting difference between the high voltage and a power supply voltage; a high voltage pump for performing a pumping operation to generate a high voltage when one of output signals of the first voltage level detector and the second voltage level detector is enabled; and a controller for receiving the output signal of the second voltage level detector, and for connecting a terminal through which the high voltage is output with the power supply voltage when the high voltage is lower than the power supply voltage.

公开(公告)号：US06885605B2

公开(公告)日：2005-04-26

申请号：US10255999

申请日：2002-09-26

Applicant: Kang Seol Lee ,  Jae Jin Lee ,  Kee Teok Park

Inventor： Kang Seol Lee ,  Jae Jin Lee ,  Kee Teok Park

IPC: H03K19/00 ,  G11C5/14 ,  G11C7/00 ,  G11C7/20 ,  G11C11/407 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4193

CPC classification number: G11C11/4074 ,  G11C7/20 ,  G11C11/4072 ,  G11C2207/2227

Abstract: A power-up signal generator uses a deep power down power-up signal, which should be in a standby state in a deep power down entry, for an initialization of other semiconductor elements in a DRAM device that operates after an internal power supply voltage is generated. The generator also uses the power-up signal, which is disabled in the deep power down entry and enabled in a deep power down exit by the internal power supply voltage. The generator may include a power-up detector for generating a power-up detection signal, a deep power down power-up signal generator for generating a deep power down power-up signal, a power-up signal generator for generating a power-up signal and a power-up controller for determining whether or not to enable the power-up signal in the deep power down entry.

Abstract translation: 上电信号发生器使用深度掉电加电信号，其将处于深功率下降条目中的待机状态，用于在内部电源电压为内部操作的DRAM器件中的其它半导体元件的初始化 生成。 发电机还使用上电信号，该信号在深度掉电输入中被禁用，并通过内部电源电压在深度断电输出中使能。 该发生器可以包括用于产生上电检测信号的上电检测器，用于产生深度掉电上电信号的深度断电上电信号发生器，用于产生上电的上电信号发生器 信号和上电控制器，用于确定是否在深度断电输入中启用上电信号。

公开(公告)号：US06765406B2

公开(公告)日：2004-07-20

申请号：US10330821

申请日：2002-12-27

Applicant: Ji Eun Jang ,  Jae Jin Lee

Inventor： Ji Eun Jang ,  Jae Jin Lee

IPC: H03K19003

CPC classification number: H05K1/0246 ,  G11C7/10 ,  G11C11/4093 ,  H03K19/0175 ,  H05K1/0286 ,  H05K1/14 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/10022

Abstract: A circuit board configured to provide multiple interfaces is disclosed. The circuit board comprises a termination slot inserted with a termination module configured to modulate circuits by applying a termination resistance and a termination voltage. If the termination module is inserted into the termination slot, the circuit board operates as a series stub terminated transceiver logic (SSTL) interface. Otherwise, the board operates as a low voltage transistor logic (LVTTL) interface. Additionally, the board comprises a switch configured to selectively connect a termination resistance to a bus. If the switch connects the termination resistance to the bus, the board operates as an SSTL interface. Otherwise, the board operates as an LVTTL interface.

Abstract translation: 公开了一种被配置为提供多个接口的电路板。 电路板包括插入有终端模块的终端插槽，其配置成通过施加终端电阻和终止电压来调制电路。 如果终端模块插入终端插槽，则电路板作为串行存根终端收发器逻辑（SSTL）接口运行。 否则，该板作为低电压晶体管逻辑（LVTTL）接口工作。 另外，电路板包括被配置为选择性地将终端电阻连接到总线的开关。 如果开关将终端电阻连接到总线，则该板作为SSTL接口工作。 否则，该板作为LVTTL接口运行。

公开(公告)号：US06759280B2

公开(公告)日：2004-07-06

申请号：US10246834

申请日：2002-09-18

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee

IPC: H01L2182

CPC classification number: H01L27/10897 ,  G11C11/4097 ,  H01L27/10885

Abstract: The present invention relates to an improved memory circuit with a divided bit-line, shared sense amplifier architecture. In a conventional divided bit-line, shared sense amplifier configuration, two adjacent memory sub-arrays are generally located between two banks of sense amplifiers and selected bit lines of the two adjacent memory sub-arrays are generally connected to metal lines with metal contacts to reduce capacitive loading. Under the present invention, some sense amplifiers from either banks of sense amplifiers are repositioned to the area between the two adjacent memory sub-arrays thereby permitting the repositioned sense amplifiers to be shared. As a result, any two adjacent memory sub-arrays share a bank of sense amplifiers. Furthermore, selected bit lines from the two adjacent memory sub-arrays are coupled to metal lines within the repositioned sense amplifiers. In addition, equilibration circuits are similarly relocated to the area between the two adjacent memory sub-arrays thereby permitting selected bit lines and metal lines to be precharged and equalized in a shorter period of time. By reducing the precharge time, faster memory access can be achieved.

Abstract translation: 本发明涉及具有分立位线，共享读出放大器结构的改进的存储电路。 在传统的分割位线，共享读出放大器配置中，两个相邻存储器子阵列通常位于两组读出放大器之间，并且两个相邻存储器子阵列的选定位线通常连接到具有金属触点的金属线 降低容性负载。 在本发明中，来自读出放大器的任意一组的一些读出放大器被重新定位到两个相邻存储器子阵列之间的区域，从而允许重新定位的读出放大器被共享。 结果，任何两个相邻的存储器子阵列共享一组读出放大器。 此外，来自两个相邻的存储器子阵列的选定的位线被耦合到重新定位的读出放大器内的金属线。 此外，平衡电路类似地重新定位到两个相邻的存储器子阵列之间的区域，从而允许在更短的时间段内对所选择的位线和金属线进行预充电和均衡。 通过减少预充电时间，可以实现更快的存储器访问。

公开(公告)号：US06525406B1

公开(公告)日：2003-02-25

申请号：US09687049

申请日：2000-10-13

Applicant: Young Suk Chung ,  Sung Sik Jang ,  Jae Jin Lee ,  Tae Heon Lee ,  Hyung Ju Lee ,  Jung Woo Lee ,  Mu Hwan Seo ,  Jae Hak Yee ,  Ku Sun Hong

Inventor： Young Suk Chung ,  Sung Sik Jang ,  Jae Jin Lee ,  Tae Heon Lee ,  Hyung Ju Lee ,  Jung Woo Lee ,  Mu Hwan Seo ,  Jae Hak Yee ,  Ku Sun Hong

IPC: H01L23495

CPC classification number: H01L23/544 ,  H01L21/4842 ,  H01L23/3114 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/28 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18301 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed is a semiconductor package and a method for manufacturing the same. A planar or substantially planar die pad is disposed within a leadframe and is connected to the leadframe by a plurality of tie bars. An perimeter of an upper and lower surface of the die pad is half-etched to increase the moisture-permeation path of the finished package. A plurality of rectangular leads extends from the leadframe toward the die pad without contacting the die pad. A silver-plating layer may be formed on the upper surface of the leadframe. A semiconductor chip is mounted on the upper surface of the die pad in the leadframe. After deflashing, the package is treated with a sulfuric (H2SO4)-based solution to restore the internal leads to their original color. Prior to singulation, the externally exposed bottom surfaces of the leads are plated with copper, gold, solder, tin, nickel, palladium, or an alloy thereof to form a predetermined thickness of a plating layer. The singulation step comprises forming a burr at a peripheral side surface of the leads in the upward direction. The finished package may be marked with a recognition mark to enable a user to more easily identify the first lead.

Abstract translation: 公开了一种半导体封装及其制造方法。 平面或基本上平面的管芯焊盘设置在引线框架内，并且通过多个连接条连接到引线框架。 芯片焊盘的上表面和下表面的周边被半蚀刻以增加成品封装的透湿路径。 多个矩形引线从引线框架朝向管芯焊盘延伸，而不接触管芯焊盘。 可以在引线框架的上表面上形成镀银层。 半导体芯片安装在引线框架中的管芯焊盘的上表面上。 在消融后，将包装用硫酸（H 2 SO 4）的溶液处理，以将内部引线恢复到其原始颜色。 在分割之前，引线的外露的底表面镀有铜，金，焊料，锡，镍，钯或其合金，以形成预定厚度的镀层。 分割步骤包括在引线的周向侧表面沿向上方向形成毛刺。 完成的包装可以标记有识别标记，以使用户能够更容易地识别第一个引线。

公开(公告)号：US06479851B1

公开(公告)日：2002-11-12

申请号：US09573070

申请日：2000-05-16

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee

IPC: H01L27108

CPC classification number: H01L27/10897 ,  G11C11/4097 ,  H01L27/10885

Abstract: The present invention relates to an improved memory circuit with a divided bit-line, shared sense amplifier architecture. In a conventional divided bit-line, shared sense amplifier configuration, two adjacent memory sub-arrays are generally located between two banks of sense amplifiers and selected bit lines of the two adjacent memory sub-arrays are generally connected to metal lines with metal contacts to reduce capacitive loading. Under the present invention, some sense amplifiers from either banks of sense amplifiers are repositioned to the area between the two adjacent memory sub-arrays thereby permitting the repositioned sense amplifiers to be shared. As a result, any two adjacent memory sub-arrays share a bank of sense amplifiers. Furthermore, selected bit lines from the two adjacent memory sub-arrays are coupled to metal lines within the repositioned sense amplifiers. In addition, equilibration circuits are similarly relocated to the area between the two adjacent memory sub-arrays thereby permitting selected bit lines and metal lines to be precharged and equalized in a shorter period of time. By reducing the precharge time, faster memory access can be achieved.

Abstract translation: 本发明涉及具有分立位线，共享读出放大器结构的改进的存储电路。 在传统的分割位线，共享读出放大器配置中，两个相邻存储器子阵列通常位于两组读出放大器之间，并且两个相邻存储器子阵列的选定位线通常连接到具有金属触点的金属线 降低容性负载。 在本发明中，来自读出放大器的任意一组的一些读出放大器被重新定位到两个相邻存储器子阵列之间的区域，从而允许重新定位的读出放大器被共享。 结果，任何两个相邻的存储器子阵列共享一组读出放大器。 此外，来自两个相邻存储器子阵列的选定位线耦合到重定位的读出放大器内的金属线。 此外，平衡电路类似地重新定位到两个相邻的存储器子阵列之间的区域，从而允许在更短的时间段内对所选择的位线和金属线进行预充电和均衡。 通过减少预充电时间，可以实现更快的存储器访问。

公开(公告)号：US5973981A

公开(公告)日：1999-10-26

申请号：US966200

申请日：1997-11-07

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee

IPC: G11C29/36 ,  G11C8/00

CPC classification number: G11C29/36

Abstract: A stress test apparatus and method for a semiconductor memory device with a plurality of memory cell arrays. The stress test apparatus comprises a plurality of plate terminals connected to one another, each of the plate terminals being connected to a plurality of storage capacitors, first and second switching elements connected in common to the plate terminals, a plate voltage generator connected to the first switching element, a stress signal generator connected to the second switching element, and a switching control signal generator for generating a switching control signal to control the first and second switching elements. According to the present invention, a cell plate voltage is applied and varied to stress the storage capacitors without driving word lines. Therefore, the storage capacitor stressing operation is simply performed, the stress test time is reduced and the cost is cut down.

Abstract translation: 一种具有多个存储单元阵列的半导体存储器件的应力测试装置和方法。 应力测试装置包括彼此连接的多个板端子，每个板端子连接到多个存储电容器，第一和第二开关元件共同连接到板端子，板电压发生器连接到第一 开关元件，连接到第二开关元件的应力信号发生器，以及用于产生开关控制信号以控制第一和第二开关元件的开关控制信号发生器。 根据本发明，施加电池板电压并改变以对存储电容器施加压力而不驱动字线。 因此，简单地进行存储电容器的应力作用，减小了应力测试时间，降低了成本。

公开(公告)号：US5767700A

公开(公告)日：1998-06-16

申请号：US673210

申请日：1996-06-27

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee

IPC: H03K19/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  H03K19/0185 ,  H03K19/017

CPC classification number: G11C7/10 ,  G11C7/22

Abstract: A pulse signal transfer unit employing post charge logic, comprising a buffering circuit for transferring data with a specified logic value through a data transfer line, a PMOS transistor for supplying a voltage from a voltage source to the data transfer line to initialize a signal on the data transfer line, and a feedback loop circuit for applying the signal on the data transfer line to the PMOS transistor for one of the first and second time periods in response to an external write drive signal to control the PMOS transistor, the second time period being longer than the first time period. According to the present invention, in the case of accessing read data with a relatively narrow pulse width and write data with a relatively wide pulse width, the pulse signal transfer unit initializes the read data at a relatively high speed and the write data at a relatively low speed to provide a signal with a wider pulse width. Therefore, the pulse signal transfer unit is capable of preventing the formation of a current path and enhancing the data processing speed.

Abstract translation: 一种采用后充电逻辑的脉冲信号传送单元，包括用于通过数据传输线传送具有指定逻辑值的数据的缓冲电路，用于将电压从电压源提供给数据传输线的PMOS晶体管，以初始化在 数据传输线路和反馈回路电路，用于响应于外部写入驱动信号将数据传输线上的信号施加到第一和第二时间段之一的PMOS晶体管，以控制PMOS晶体管，第二时间段为 比第一个时间段长。 根据本发明，在以相对窄的脉冲宽度访问读取数据并写入具有相对较宽的脉冲宽度的数据的情况下，脉冲信号传送单元以相对较高的速度初始化读取的数据，并且相对地写入数据 低速提供具有更宽脉冲宽度的信号。 因此，脉冲信号传送单元能够防止形成电流路径并提高数据处理速度。