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257 条记录 (耗时 0.039 秒)

    Profile of flash memory cells
    41.
    发明授权
    Profile of flash memory cells 有权
    闪存单元简介

    公开(公告)号：US07928499B2

    公开(公告)日：2011-04-19

    申请号：US11715229

    申请日：2007-03-07

    申请人： Shih-Chang Liu ,  Chu-Wei Chang ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

    发明人： Shih-Chang Liu ,  Chu-Wei Chang ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

    摘要： A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate.

    摘要翻译： 半导体结构包括半导体衬底; 半导体衬底上的隧道层; 邻近隧道层的源区; 和隧道层上的浮动栅极。 浮动门包括具有上部和下部的第一边缘，其中下部从上部凹进。 半导体结构还包括在浮置栅极上的阻挡层，其中阻挡层具有面向与浮动栅极的第一边缘相同方向的第一边缘。

    Method of forming planarized coatings on contact hole patterns of various duty ratios
    44.
    再颁专利
    Method of forming planarized coatings on contact hole patterns of various duty ratios 有权
    在各种占空比的接触孔图案上形成平面化涂层的方法

    公开(公告)号：USRE41697E1

    公开(公告)日：2010-09-14

    申请号：US11235648

    申请日：2005-09-26

    申请人： Chia-Tung Ho ,  Feng-Jia Shih ,  Jieh-Jang Chen ,  Ching-Sen Kuo ,  Shih-Chi Fu ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

    发明人： Chia-Tung Ho ,  Feng-Jia Shih ,  Jieh-Jang Chen ,  Ching-Sen Kuo ,  Shih-Chi Fu ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76808 ,  G03F7/0035 ,  G03F7/09 ,  G03F7/16 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

    摘要： A method of forming a planarized photoresist coating on a substrate having holes with different duty ratios is described. A first photoresist preferably comprised of a Novolac resin and a diazonaphthoquinone photoactive compound is coated on a substrate and baked at or slightly above its Tg so that it reflows and fills the holes. The photoresist is exposed without a mask at a dose that allows the developer to thin the photoresist to a recessed depth within the holes. After the photoresist is hardened with a 250° C. bake, a second photoresist is coated on the substrate to form a planarized film with a thickness variation of less than 50 Angstroms between low and high duty ratio hole regions. One application is where the second photoresist is used to form a trench pattern in a via first dual damascene method. Secondly, the method is useful in fabricating MIM capacitors.

    摘要翻译： 描述了在具有不同占空比的孔的基板上形成平坦化光致抗蚀剂涂层的方法。 优选将包含酚醛清漆树脂和重氮萘醌光敏化合物的第一光致抗蚀剂涂覆在基材上并在其Tg以上或略高于其Tg的温度下使其回流并填充孔。 以允许显影剂将光致抗蚀剂减薄到孔内的凹陷深度的剂量，光刻胶不用掩模曝光。 在250℃烘烤后光致抗蚀剂硬化后，在基板上涂覆第二光致抗蚀剂，以形成厚度变化小于50埃的低和高占空比孔区域的平坦化膜。 一种应用是第二光致抗蚀剂用于以通孔第一双镶嵌方法形成沟槽图案。 其次，该方法在制造MIM电容器方面是有用的。

    Gated Semiconductor Device and Method of Fabricating Same
    45.
    发明申请
    Gated Semiconductor Device and Method of Fabricating Same 有权
    门控半导体器件及其制造方法

    公开(公告)号：US20100171167A1

    公开(公告)日：2010-07-08

    申请号：US12723381

    申请日：2010-03-12

    申请人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

    发明人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

    IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/788

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

    摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

    摘要翻译： 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。

    Split-gate memory cells and fabrication methods thereof
    46.
    发明授权
    Split-gate memory cells and fabrication methods thereof 失效
    分离栅存储单元及其制造方法

    公开(公告)号：US07667261B2

    公开(公告)日：2010-02-23

    申请号：US11785382

    申请日：2007-04-17

    申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.

    摘要翻译： 分离栅存储单元及其制造方法。 分离栅存储器单元包括沿着第一方向在半导体衬底上形成的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。 活动区域的顶层低于隔离区域的顶层。 一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。 一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

    Split-gate memory cells and fabrication methods thereof
    47.
    发明授权
    Split-gate memory cells and fabrication methods thereof 有权
    分离栅存储单元及其制造方法

    公开(公告)号：US07652318B2

    公开(公告)日：2010-01-26

    申请号：US11592290

    申请日：2006-11-03

    申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

    摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。 一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。 一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

    Magnetic memory cells and manufacturing methods
    50.
    发明授权
    Magnetic memory cells and manufacturing methods 有权
    磁记忆体和制造方法

    公开(公告)号：US07554145B2

    公开(公告)日：2009-06-30

    申请号：US11610760

    申请日：2006-12-14

    申请人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    发明人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

    IPC分类号： H01L29/76

    CPC分类号： H01L43/12 ,  H01L27/228

    摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

    摘要翻译： 改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。 通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。 然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。 然后可以在掩模层和导电通孔上形成导电存储器线。