公开(公告)号：US20090200604A1

公开(公告)日：2009-08-13

申请号：US10597288

申请日：2004-01-22

申请人： Dureseti Chidambarrao ,  Jochen Beintner ,  Ramachandra Divakaruni

发明人： Dureseti Chidambarrao ,  Jochen Beintner ,  Ramachandra Divakaruni

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78642 ,  H01L21/2257 ,  H01L29/66787

摘要： A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.

摘要翻译： 描述了一种新型的具有低接触电阻的高密度垂直Fin-FET器件。 这些垂直Fin-FET器件具有用作晶体管体的垂直硅“鳍”（12A）。 掺杂的源极和漏极区域（26A，28A）分别形成在鳍片（12A）的底部和顶部。 盖板（24A，24B）沿翅片的侧壁形成。 当适当的偏压被施加到栅极（24A，24B）时，电流垂直地流过源极和漏极区域（26A，28A）之间的鳍片（12A）。 描述了同时形成pFET，nFET，多鳍，单鳍，多栅极和双栅极垂直鳍FET的集成工艺。

公开(公告)号：US07410844B2

公开(公告)日：2008-08-12

申请号：US11333108

申请日：2006-01-17

申请人： Yujun Li ,  Kenneth T. Settlemyer, Jr. ,  Jochen Beintner

发明人： Yujun Li ,  Kenneth T. Settlemyer, Jr. ,  Jochen Beintner

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L21/30608 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66772 ,  H01L29/66818 ,  H01L29/785

摘要： A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.

摘要翻译： 提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。 产生基于Si的材料基座，其顶表面和其侧壁的方向定位成与基座和支撑构件的选定结晶平面基本平行。 用包含氢氧化铵的各向异性溶液湿式蚀刻基座。 基座的侧壁变小，在基座上形成截面减小的部分。 选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

公开(公告)号：US07346887B2

公开(公告)日：2008-03-18

申请号：US11164076

申请日：2005-11-09

申请人： Lars W. Liebmann ,  Jochen Beintner

发明人： Lars W. Liebmann ,  Jochen Beintner

IPC分类号： G06F17/50

CPC分类号： G03F1/70

摘要： The present invention is directed to a method for conversion of an integrated circuit design into a set of masks for fabrication of an integrated circuit that optimizes use of an edge based image transfer mask process.

摘要翻译： 本发明涉及一种用于将集成电路设计转换成用于制造集成电路的一组掩模的方法，该集成电路优化了基于边缘的图像传送掩模处理的使用。

公开(公告)号：US20070167024A1

公开(公告)日：2007-07-19

申请号：US11333109

申请日：2006-01-17

申请人： Yujun Li ,  Kenneth Settlemyer ,  Jochen Beintner

发明人： Yujun Li ,  Kenneth Settlemyer ,  Jochen Beintner

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/30608 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7853

摘要： A method is presented for fabricating a non-planar field effect device. The method includes the production of a Si based material Fin structure that has a top surface substantially in parallel with a {111} crystallographic plane of the Si Fin structure, and the etching of the Si Fin structure with a solution which contains ammonium hydroxide (NH4OH). In this manner, due to differing etch rates in ammonium hydroxide of various Si based material crystallographic planes, the corners on the Fin structure become clipped, and angles between the horizontal and vertical planes of the Fin structure increase. A FinFET device with clipped, or rounded, corners is then fabricated to completion. In a typical embodiment the FinFET device is selected to be a silicon-on-insulator (SOI) device.

摘要翻译： 提出了一种用于制造非平面场效应器件的方法。 该方法包括生产Si基材料Fin结构，其具有与Si Fin结构的{111}晶面大致平行的顶表面，并且用含有氢氧化铵（NH）的溶液蚀刻Si Fin结构 4 OH）。 以这种方式，由于各种Si基材料结晶面的氢氧化铵中的蚀刻速率不同，Fin结构上的拐角被限制，Fin结构的水平和垂直平面之间的角度增加。 然后制造具有夹角或圆角的FinFET器件以完成。 在典型的实施例中，FinFET器件被选择为绝缘体上硅（SOI）器件。

公开(公告)号：US20070106972A1

公开(公告)日：2007-05-10

申请号：US11164076

申请日：2005-11-09

申请人： Lars Liebmann ,  Jochen Beintner

发明人： Lars Liebmann ,  Jochen Beintner

IPC分类号： G06F17/50 ,  G06F19/00 ,  G03F1/00

CPC分类号： G03F1/70

摘要： The present invention is directed to a method for conversion of an integrated circuit design into a set of masks for fabrication of an integrated circuit that optimizes use of an edge based image transfer mask process.

摘要翻译： 本发明涉及一种用于将集成电路设计转换成用于制造集成电路的一组掩模的方法，该集成电路优化了基于边缘的图像传送掩模处理的使用。

公开(公告)号：US07101755B2

公开(公告)日：2006-09-05

申请号：US10912005

申请日：2004-08-05

申请人： Jochen Beintner

发明人： Jochen Beintner

IPC分类号： H01L21/8242

CPC分类号： H01L27/10891 ,  H01L27/10864 ,  H01L27/10894

摘要： A method for processing a semiconductor device includes providing the semiconductor device including a deep trench transistor in an array area and a shallow trench isolation oxide in a support area, wherein a pad oxide and pad nitride are sequentially formed on a semiconductor substrate. The method includes stripping the pad nitride, depositing an array top oxide layer over the pad oxide formed on the semiconductor substrate in the array area and the support area, and planarizing the array top oxide to a top of the shallow trench isolation oxide in the support area and to a deep trench poly stud of the deep trench transistor in the array area. The method further includes forming a wordline stack comprising a nitride layer, a gate conductor and an insulator, and etching the array top oxide, forming a passing wordline bridge through the array area supported on the shallow trench isolation oxide.

摘要翻译： 一种用于处理半导体器件的方法包括在支撑区域中提供包括阵列区域中的深沟槽晶体管和浅沟槽隔离氧化物的半导体器件，其中在半导体衬底上依次形成衬垫氧化物和衬垫氮化物。 该方法包括剥离衬垫氮化物，在阵列区域和支撑区域中形成在半导体衬底上的衬垫氧化物上沉积阵列顶部氧化物层，并将阵列顶部氧化物平坦化到支撑体中浅沟槽隔离氧化物的顶部 区域和阵列区域中的深沟槽晶体管的深沟槽多芯柱。 该方法还包括形成包括氮化物层，栅极导体和绝缘体的字线堆叠，并蚀刻阵列顶部氧化物，形成通过支撑在浅沟槽隔离氧化物上的阵列区域的通过字线桥。

公开(公告)号：US20060128111A1

公开(公告)日：2006-06-15

申请号：US11351801

申请日：2006-02-10

申请人： Jochen Beintner ,  Gary Bronner ,  Ramachandra Divakaruni ,  Byeong Kim

发明人： Jochen Beintner ,  Gary Bronner ,  Ramachandra Divakaruni ,  Byeong Kim

IPC分类号： H01L21/76

CPC分类号： H01L29/66628 ,  H01L21/76243 ,  H01L21/76251 ,  H01L29/1054 ,  H01L29/41783 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/78687 ,  Y10S438/938

摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.

摘要翻译： 本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及 包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。 本发明还提供了一种形成这种结构的方法。 在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

公开(公告)号：US06967384B2

公开(公告)日：2005-11-22

申请号：US10733381

申请日：2003-12-12

申请人： Jochen Beintner ,  Dureseti Chidambarrao

发明人： Jochen Beintner ,  Dureseti Chidambarrao

IPC分类号： C23C16/02 ,  C23C16/24 ,  H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/3205 ,  H01L29/49 ,  H01L29/772 ,  H01L21/8232

CPC分类号： C23C16/24 ,  C23C16/0272 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/28035 ,  H01L21/32055 ,  H01L29/4925

摘要： A method of forming a semiconductor structure (and the resulting structure), includes providing a nitride layer between a silicon-containing layer and a polysilicon layer.

公开(公告)号：US06967147B1

公开(公告)日：2005-11-22

申请号：US09714356

申请日：2000-11-16

申请人： Helmut Horst Tews ,  Jochen Beintner

发明人： Helmut Horst Tews ,  Jochen Beintner

IPC分类号： H01L20060101 ,  H01L21/265 ,  H01L21/28 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/06

CPC分类号： H01L21/823462 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/10873 ,  Y10S438/981

摘要： Process for forming dual gate oxides for DRAMS by incorporating different thicknesses of gate oxides by using nitrogen implantation. Either angled nitrogen implantation or nitride spacers is used to create a “shadow effect” or area, which limits the nitrogen dose close to the edges of the active area. The reduction of nitrogen dose leads to an increased gate oxide thickness at the active area (AA) adjacent to the shallow trench, increases the threshold of the parasitic corner device and reduces sub Vt (threshold voltage) and junction leakage.

摘要翻译： 用于通过使用氮注入并入不同厚度的栅极氧化物来形成用于DRAMS的双栅极氧化物的工艺。 使用倾斜的氮气注入或氮化物间隔物来产生“阴影效应”或区域，这限制了接近有效区域边缘的氮剂量。 氮剂量的减少导致在与浅沟槽相邻的有源区（AA）处的栅极氧化物厚度增加，增加了寄生角装置的阈值并且减小了副Vt（阈值电压）和结漏电。

公开(公告)号：US06960514B2

公开(公告)日：2005-11-01

申请号：US10803395

申请日：2004-03-18

申请人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

发明人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

摘要翻译： 对于给定的栅极长度，对于晶体管导通电流的增加，晶体管串联电阻的降低和接触电阻的降低，用于场效应晶体管的改进的投池形有源区域。 投球形有源区结构包括形成在衬底中的至少两个浅沟槽绝缘体（STI）结构，其限定有源区域结构，其包括宽度比底部宽的加宽顶部部分。 还描述了一种用于形成改进的捕鱼器活性区域的改进的制造方法，其实现了形成STI结构图形的步骤，随后是将基板材料迁移到图案的至少部分中的步骤，从而形成活动的加宽顶部 区域结构。 本发明的制造方法在不使用光刻的情况下形成投手型有源区域，因此不受光刻工具的最小基准规则的限制。