公开(公告)号：US07683428B2

公开(公告)日：2010-03-23

申请号：US10597288

申请日：2004-01-22

申请人： Dureseti Chidambarrao ,  Jochen Beintner ,  Ramachandra Divakaruni

发明人： Dureseti Chidambarrao ,  Jochen Beintner ,  Ramachandra Divakaruni

IPC分类号： H01L27/108

CPC分类号： H01L29/78642 ,  H01L21/2257 ,  H01L29/66787

摘要： A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.

摘要翻译： 描述了一种新型的具有低接触电阻的高密度垂直Fin-FET器件。 这些垂直Fin-FET器件具有用作晶体管体的垂直硅“鳍”（12A）。 掺杂的源极和漏极区域（26A，28A）分别形成在鳍片（12A）的底部和顶部。 盖板（24A，24B）沿翅片的侧壁形成。 当适当的偏压被施加到栅极（24A，24B）时，电流垂直地流过源极和漏极区域（26A，28A）之间的鳍片（12A）。 描述了同时形成pFET，nFET，多鳍，单鳍，多栅极和双栅极垂直鳍FET的集成工艺。

公开(公告)号：US20050121412A1

公开(公告)日：2005-06-09

申请号：US10730234

申请日：2003-12-09

申请人： Jochen Beintner ,  Dureseti Chidambarrao ,  Yujun Li ,  Kenneth Settlemyer

发明人： Jochen Beintner ,  Dureseti Chidambarrao ,  Yujun Li ,  Kenneth Settlemyer

IPC分类号： H01L21/308 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786 ,  B44C1/22 ,  C25F3/00

CPC分类号： H01L29/785 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/66795

摘要： A method of forming integrated circuits having FinFET transistors includes a method of forming sub-lithographic fins, in which a mask defining a block of silicon including a pair of fins in reduced in width or pulled back by the thickness of one fin on each side, after which a second mask is formed around the first mask, so that after the first mask is removed, an aperture remains in the second mask having the width of the separation distance between the pair of fins. When the silicon is etched through the aperture, the fins are protected by the second mask, thereby defining fin thickness by the pullback step. An alternative method uses lithography of opposite polarity, first defining the central etch aperture between the two fins lithographically, then expanding the width of the aperture by a pullback step, so that filling the widened aperture with an etch-resistant plug defines the outer edges of the pair of fins, thereby setting the fin width without an alignment kstep.

摘要翻译： 一种形成具有FinFET晶体管的集成电路的方法包括形成次光刻鳍片的方法，其中限定包含一对鳍片的硅块的掩模，所述掩模的宽度被减小或者被拉回每边的一个鳍片的厚度， 之后在第一掩模周围形成第二掩模，使得在去除第一掩模之后，在第二掩模中保留具有一对散热片之间的间隔距离的宽度的孔。 当通过孔蚀刻硅时，翅片被第二掩模保护，从而通过拉回步骤限定翅片厚度。 一种替代方法是使用相反极性的光刻法，首先在两个散热片之间光刻地限定中心蚀刻孔径，然后通过拉回步骤扩大孔径的宽度，以便用耐蚀刻塞子填充加宽的孔径限定了 一对翅片，从而设置翅片宽度而没有对准kstep。

公开(公告)号：US20090200604A1

公开(公告)日：2009-08-13

申请号：US10597288

申请日：2004-01-22

申请人： Dureseti Chidambarrao ,  Jochen Beintner ,  Ramachandra Divakaruni

发明人： Dureseti Chidambarrao ,  Jochen Beintner ,  Ramachandra Divakaruni

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78642 ,  H01L21/2257 ,  H01L29/66787

摘要： A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.

摘要翻译： 描述了一种新型的具有低接触电阻的高密度垂直Fin-FET器件。 这些垂直Fin-FET器件具有用作晶体管体的垂直硅“鳍”（12A）。 掺杂的源极和漏极区域（26A，28A）分别形成在鳍片（12A）的底部和顶部。 盖板（24A，24B）沿翅片的侧壁形成。 当适当的偏压被施加到栅极（24A，24B）时，电流垂直地流过源极和漏极区域（26A，28A）之间的鳍片（12A）。 描述了同时形成pFET，nFET，多鳍，单鳍，多栅极和双栅极垂直鳍FET的集成工艺。

公开(公告)号：US06967384B2

公开(公告)日：2005-11-22

申请号：US10733381

申请日：2003-12-12

申请人： Jochen Beintner ,  Dureseti Chidambarrao

发明人： Jochen Beintner ,  Dureseti Chidambarrao

IPC分类号： C23C16/02 ,  C23C16/24 ,  H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/3205 ,  H01L29/49 ,  H01L29/772 ,  H01L21/8232

CPC分类号： C23C16/24 ,  C23C16/0272 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/28035 ,  H01L21/32055 ,  H01L29/4925

摘要： A method of forming a semiconductor structure (and the resulting structure), includes providing a nitride layer between a silicon-containing layer and a polysilicon layer.

公开(公告)号：US20050130364A1

公开(公告)日：2005-06-16

申请号：US10733381

申请日：2003-12-12

申请人： Jochen Beintner ,  Dureseti Chidambarrao

发明人： Jochen Beintner ,  Dureseti Chidambarrao

IPC分类号： C23C16/02 ,  C23C16/24 ,  H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/3205 ,  H01L29/49 ,  H01L29/76 ,  H01L21/336

CPC分类号： C23C16/24 ,  C23C16/0272 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/28035 ,  H01L21/32055 ,  H01L29/4925

摘要： A method of forming a semiconductor structure (and the resulting structure), includes providing a nitride layer between a silicon-containing layer and a polysilicon layer.

摘要翻译： 形成半导体结构的方法（及其结果）包括在含硅层和多晶硅层之间设置氮化物层。

公开(公告)号：US20080176365A1

公开(公告)日：2008-07-24

申请号：US12077973

申请日：2008-03-24

申请人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

发明人： Huilong Zhu ,  Bruce B. Doris ,  Xinlin Wang ,  Jochen Beintner ,  Ying Zhang ,  Philip J. Oldiges

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

摘要： A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.

摘要翻译： 提供了一种制造门控半导体器件的方法。 这种方法可以包括图案化衬底的单晶半导体区域，以在与衬底的主表面平行的横向方向上延伸并且沿至少基本上垂直且至少基本垂直于主表面的方向延伸，半导体 区域具有第一侧和第二侧，例如远离第一侧。 第一栅极可以形成在第一侧上，第一栅极在横向上具有第一栅极长度。 第二栅极可以形成在第二侧上，第二栅极在横向上具有与第一栅极长度不同的第二栅极长度。 在一个实施例中，第二栅极长度可以比​​第一栅极长度短。 在一个实施例中，第一栅极可以主要由多晶硅锗组成，第二栅极可以由多晶硅组成。

公开(公告)号：US07129564B2

公开(公告)日：2006-10-31

申请号：US11059819

申请日：2005-02-17

申请人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Shane Wrschka

发明人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Shane Wrschka

IPC分类号： H01L31/117

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/665 ,  Y10S438/933

摘要： The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.

摘要翻译： 本文公开的形成缺口栅极MOSFET的结构和方法解决了诸如器件可靠性的问题。 栅电介质（例如栅极氧化物）形成在半导体衬底上的有源区的表面上，优选由隔离沟槽区限定。 然后在栅极电介质上沉积多晶硅层。 该步骤之后是沉积一层硅锗）（SiGe）。 然后横向蚀刻多晶硅层的侧壁，对SiGe层有选择性，以产生刻蚀的栅极导体结构，其中SiGe层比下面的多晶硅层宽。 侧壁间隔物优选形成在SiGe层和多晶硅层的侧壁上。 硅化物层优选从沉积在SiGe层上的多晶硅层形成为自对准硅化物，以降低栅极导体的电阻。 优选在完成晶体管时执行一个或多个其它处理步骤（例如源极和漏极注入，延伸注入和袖带轻掺杂漏极（LDD）注入），栅极导体堆叠掺杂和硅化。

公开(公告)号：US07087952B2

公开(公告)日：2006-08-08

申请号：US10978951

申请日：2004-11-01

申请人： Huilong Zhu ,  Bruce B. Doris ,  Jochen Beintner

发明人： Huilong Zhu ,  Bruce B. Doris ,  Jochen Beintner

IPC分类号： H01L29/788

CPC分类号： H01L29/78684 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7881

摘要： A non-volatile storage cell in a Fin Field Effect Transistor (FinFET) and a method of forming an Integrated Circuit (IC) chip including the non-volatile storage cell. Each FET includes a control gate along one side of a semiconductor (e.g., silicon) fin, a floating gate along an opposite of the fin and a program gate alongside the floating gate. Control gate device thresholds are adjusted by adjusting charge on the floating gate.

摘要翻译： Fin场效应晶体管（FinFET）中的非易失性存储单元以及形成包括非易失性存储单元的集成电路（IC）芯片的方法。 每个FET包括沿着半导体（例如硅）翅片的一侧的控制栅极，沿着鳍片的相对的浮动栅极和沿着浮动栅极的编程栅极。 通过调节浮动栅极上的电荷来调节控制栅极器件的阈值。

公开(公告)号：US20060024930A1

公开(公告)日：2006-02-02

申请号：US11235330

申请日：2005-09-26

申请人： Helmut Tews ,  Jochen Beintner

发明人： Helmut Tews ,  Jochen Beintner

IPC分类号： H01L21/425

CPC分类号： H01L21/823462 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L21/823481 ,  H01L27/0629 ,  H01L27/10873 ,  Y10S438/981

摘要： A semiconductor body has a first portion, a second portion, and an active area located between the first portion and the second portion. The first portion and the second portion are a shallow trench isolation region having an exposed surface extending above the surface of the active area. A first ion implantation is performed at a first angle such that a first shaded area defined by the exposed surface of the first portion and the first angle is exposed to fewer ions than a first unshaded area. A second ion implantation is performed at a second angle such that a second shaded area defined by the exposed surface of the second portion and the second angle is exposed to fewer ions than a second unshaded area.

摘要翻译： 半导体本体具有位于第一部分和第二部分之间的第一部分，第二部分和有源区域。 第一部分和第二部分是具有在有源区域的表面上方延伸的暴露表面的浅沟槽隔离区域。 以第一角度执行第一离子注入，使得由第一部分的暴露表面限定的第一阴影区域和第一角度暴露于比第一未阴影区域更少的离子。 以第二角度执行第二离子注入，使得由第二部分的暴露表面限定的第二阴影区域和第二角度暴露于比第二未阴影区域更少的离子。

公开(公告)号：US06987042B2

公开(公告)日：2006-01-17

申请号：US10250046

申请日：2003-05-30

申请人： Jochen Beintner ,  Naim Moumen ,  Porshia S. Wrschka

发明人： Jochen Beintner ,  Naim Moumen ,  Porshia S. Wrschka

IPC分类号： H01L21/8242

CPC分类号： H01L27/1087 ,  H01L21/30604 ,  H01L29/66181 ,  H01L29/945

摘要： A method of forming collar isolation for a trench storage memory cell structure is provided in which amorphous Si (a:Si) and silicon germanium (SiGe) are first formed into a trench structure. An etching process that is selective to a:Si as compared to SiGe is employed in defining the regions in which the collar isolation will be formed. The selective etching process employed in the present invention is a wet etch process that includes etching with HF, rinsing, etching with NH4OH, rinsing, and drying with a monohydric alcohol such as isopropanol. The sequence of NH4OH etching and rinsing may be repeated any number of times. The conditions used in the selective etching process of the present invention are capable of etching a:Si at a faster rate than SiGe.

摘要翻译： 提供了一种形成沟槽存储单元结构的套环隔离的方法，其中首先将非晶硅（a：Si）和硅锗（SiGe）形成沟槽结构。 与SiGe相比，对a：Si有选择性的蚀刻工艺用于限定将形成套环隔离的区域。 在本发明中采用的选择性蚀刻方法是湿式蚀刻工艺，其包括用HF蚀刻，漂洗，用NH 4 OH蚀刻，漂洗和用一元醇如异丙醇干燥。 NH 4 OH蚀刻和漂洗的顺序可以重复任意次数。 在本发明的选择性蚀刻工艺中使用的条件能够以比SiGe更快的速度蚀刻Si。