公开(公告)号：US07042038B2

公开(公告)日：2006-05-09

申请号：US10653889

申请日：2003-09-04

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

摘要翻译： 在其中形成有用于选择构成DRAM的存储单元的DRAM存储单元的金属绝缘体半导体场效应晶体管（MISFET）（Qs）的有源区域（L）被布置成具有岛状图案， 在半导体衬底（1）的一个主表面上沿X方向线性地延伸。 存储单元选择MISFET（Qs）具有在半导体衬底（1）的主表面上沿着Y方向延伸的绝缘栅电极（字线WL），沿着其长度保持相同的宽度， 栅电极被布置成以比所述宽度窄的预定距离或间距与与其相邻的另一个栅电极（7）（字线WL）相对。 此外，位线（BL）以这样的方式设置在存储单元选择MISFET（Qs）上，使得位线在半导体衬底（1）的主表面上沿X方向以相同的宽度延伸，并且 以比所述宽度更宽的距离或间距来对置其相邻位线（BL）。

公开(公告)号：US20050042822A1

公开(公告)日：2005-02-24

申请号：US10950595

申请日：2004-09-28

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

IPC分类号： H01L21/265 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/8249 ,  H01L21/8234

CPC分类号： H01L21/2652 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53257 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10894 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed.

摘要翻译： 在制造具有MISFET的半导体集成电路器件的工艺中，为了通过减少热处理步骤的数量来实现MISFET的源极/漏极与半导体衬底之间的浅结，可以将所有导电膜沉积 在形成MISFET之后的步骤中，在500℃以下的温度下沉积半导体基板。 此外，要沉积在半导体衬底上的所有绝缘膜在形成MISFET之后的步骤中在500℃或更低的温度下沉积。

公开(公告)号：US06815762B2

公开(公告)日：2004-11-09

申请号：US09416959

申请日：1999-10-13

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

IPC分类号： H01L29788

CPC分类号： H01L21/76897 ,  H01L21/2652 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76889 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53257 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10894 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed.

摘要翻译： 在制造具有MISFET的半导体集成电路器件的工艺中，为了通过减少热处理步骤的数量来实现MISFET的源极/漏极与半导体衬底之间的浅结，可以将所有导电膜沉积 在形成MISFET之后的步骤中，在500℃以下的温度下沉积半导体基板。 此外，要沉积在半导体衬底上的所有绝缘膜在形成MISFET之后的步骤中在500℃或更低的温度下沉积。

公开(公告)号：US08294225B2

公开(公告)日：2012-10-23

申请号：US12407414

申请日：2009-03-19

申请人： Shuntaro Machida ,  Hiroyuki Enomoto ,  Yoshitaka Tadaki

发明人： Shuntaro Machida ,  Hiroyuki Enomoto ,  Yoshitaka Tadaki

IPC分类号： H01L21/00

CPC分类号： B06B1/0292 ,  Y10T29/49005

摘要： This invention provides a technique whereby, even if a step is produced by splitting a lower electrode into component elements, resistance increase of an upper electrode, damage to a membrane and decrease of dielectric strength between an upper electrode and the lower electrode, are reduced. In an ultrasonic transducer comprising plural lower electrodes, an insulation film covering the lower electrodes, plural hollow parts formed to overlap the lower electrodes on the insulation film, an insulation film filling the gaps among the hollow parts, an insulation film covering the hollow parts and insulation film, plural upper electrodes formed to overlap the hollow parts on the insulation film and plural interconnections joining them, the surfaces of the hollow parts and insulation film are flattened to the same height.

摘要翻译： 本发明提供一种技术，即使通过将下部电极分割成成分元件而产生台阶，也能够降低上部电极的电阻增加，膜的损伤以及上部电极与下部电极之间的介电强度的降低。 在包括多个下电极的超声波换能器中，覆盖下电极的绝缘膜，形成为与绝缘膜上的下电极重叠的多个中空部，填充中空部之间的间隙的绝缘膜，覆盖中空部的绝缘膜， 绝缘膜，形成为与绝缘膜上的中空部分重叠的多个上电极和连接它们的多个互连，中空部分和绝缘膜的表面被平坦化到相同的高度。

公开(公告)号：US07512038B2

公开(公告)日：2009-03-31

申请号：US11671040

申请日：2007-02-05

申请人： Shuntaro Machida ,  Hiroyuki Enomoto ,  Yoshitaka Tadaki

发明人： Shuntaro Machida ,  Hiroyuki Enomoto ,  Yoshitaka Tadaki

IPC分类号： H04R19/00

CPC分类号： B06B1/0292 ,  Y10T29/49005

摘要： This invention provides a technique whereby, even if a step is produced by splitting a lower electrode into component elements, resistance increase of an upper electrode, damage to a membrane and decrease of dielectric strength between an upper electrode and the lower electrode, are reduced. In an ultrasonic transducer comprising plural lower electrodes, —an insulation film covering the lower electrodes, —plural hollow parts formed to overlap the lower electrodes on the insulation film, —an insulation film filling the gaps among the hollow parts, an insulation film covering the hollow parts and insulation film, plural upper electrodes formed to overlap the hollow parts on the insulation film and plural interconnections joining them, —the surfaces of the hollow parts and insulation film are flattened to the same height.

摘要翻译： 本发明提供一种技术，即使通过将下部电极分割成成分元件而产生台阶，也能够降低上部电极的电阻增加，膜的损伤以及上部电极与下部电极之间的介电强度的降低。 在包括多个下电极的超声波换能器中， - 覆盖下电极的绝缘膜， - 形成为与绝缘膜上的下电极重叠的 - 中空部分， - 填充中空部分之间的间隙的绝缘膜，覆盖 中空部分和绝缘膜，形成为与绝缘膜上的中空部分重叠的多个上电极和连接它们的多个互连， - 中空部分和绝缘膜的表面被平坦化到相同的高度。

公开(公告)号：US20070052093A1

公开(公告)日：2007-03-08

申请号：US11489612

申请日：2006-07-20

申请人： Shuntaro Machida ,  Hiroyuki Enomoto ,  Yoshitaka Tadaki ,  Tatsuya Nagata

发明人： Shuntaro Machida ,  Hiroyuki Enomoto ,  Yoshitaka Tadaki ,  Tatsuya Nagata

IPC分类号： H01L23/48

CPC分类号： B06B1/0292

摘要： Disclosed is an improved construction of an ultrasonic transducer, wherein a charge is not easily injected into an insulating film even when the bottom of a membrane comes in contact with a lower electrode, and a manufacturing method thereof without using the wafer laminating technique. The ultrasonic transducer includes a lower electrode; a cavity layer formed on the first electrode; an insulating film covering the cavity layer; and an upper electrode formed on the insulating film, wherein, the cavity layer includes projections formed into an insulating film protruded from the cavity layer. In addition, an opening is formed into the upper electrode, and this upper electrode having the opening formed therein is deposited at a position not being superposed with the projections of the insulating film when seen from the top.

摘要翻译： 公开了一种超声换能器的改进结构，其中即使膜的底部与下电极接触，电荷也不容易注入到绝缘膜中，并且其制造方法不使用晶片层压技术。 超声波换能器包括下电极; 形成在所述第一电极上的空腔层; 覆盖空腔层的绝缘膜; 以及形成在绝缘膜上的上电极，其中，所述空腔层包括形成为从所述空腔层突出的绝缘膜的突起。 此外，在上部电极中形成开口，并且其上形成有开口的该上部电极沉积在从顶部观察时不与绝缘膜的突起重叠的位置。

公开(公告)号：US06649956B2

公开(公告)日：2003-11-18

申请号：US10227799

申请日：2002-08-27

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

IPC分类号： H01L2972

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

公开(公告)号：US06483136B1

公开(公告)日：2002-11-19

申请号：US09446302

申请日：2000-04-14

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

IPC分类号： H01L2972

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

摘要翻译： 在其中形成有用于选择构成DRAM的存储单元的DRAM存储单元的金属绝缘体半导体场效应晶体管（MISFET）（Qs）的有源区域（L）被布置成具有岛状图案， 在半导体衬底（1）的一个主表面上沿X方向线性地延伸。 存储单元选择MISFET（Qs）具有在半导体衬底（1）的主表面上沿着Y方向延伸的绝缘栅电极（字线WL），沿着其长度保持相同的宽度， 栅电极被布置成以比所述宽度窄的预定距离或间距与与其相邻的另一个栅电极（7）（字线WL）相对。 此外，位线（BL）以这样的方式设置在存储单元选择MISFET（Qs）上，使得位线在半导体衬底（1）的主表面上沿X方向以相同的宽度延伸，并且 以比所述宽度更宽的距离或间距来对置其相邻位线（BL）。

公开(公告)号：US06291847B1

公开(公告)日：2001-09-18

申请号：US09159754

申请日：1998-09-24

申请人： Kiyonori Ohyu ,  Makoto Ohkura ,  Aritoshi Sugimoto ,  Yoshitaka Tadaki ,  Makoto Ogasawara ,  Masashi Horiguchi ,  Norio Hasegawa ,  Shinichi Fukada

发明人： Kiyonori Ohyu ,  Makoto Ohkura ,  Aritoshi Sugimoto ,  Yoshitaka Tadaki ,  Makoto Ogasawara ,  Masashi Horiguchi ,  Norio Hasegawa ,  Shinichi Fukada

IPC分类号： H01L27108

CPC分类号： H01L27/10897 ,  H01L27/10814 ,  H01L27/10894

摘要： A field oxide film 3 in a region where relief cells are formed is made wider than the field oxide film 3 in a region where normal memory cells are formed thereby to make a field relaxation layer 8r of the relief cells deeper than the field relaxation layer 8 of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.

摘要翻译： 在形成正常存储单元的区域中，形成有浮雕单元的区域中的场氧化膜3比场氧化膜3宽，使得浮雕单元的场弛豫层8r比场弛豫层8更深 的正电池，并且补充电池的源极和漏极（n型半导体区域）的耗尽层变宽以削弱结场。

公开(公告)号：US5981369A

公开(公告)日：1999-11-09

申请号：US865864

申请日：1997-05-30

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L21/44

CPC分类号： H01L21/823871 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/76849 ,  H01L21/76853 ,  H01L27/10855 ,  H01L27/10894

摘要： In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed.

摘要翻译： 在制造具有MISFET的半导体集成电路器件的工艺中，为了通过减少热处理步骤的数量来实现MISFET的源极/漏极与半导体衬底之间的浅结，可以将所有导电膜沉积 在形成MISFET之后的步骤中，在半导体基板上淀积5​​00℃以下的温度。 此外，要沉积在半导体衬底上的所有绝缘膜在形成MISFET之后的步骤中在500℃或更低的温度下沉积。