公开(公告)号：US20050244046A1

公开(公告)日：2005-11-03

申请号：US11171376

申请日：2005-07-01

申请人： Ichiro Yamamoto

发明人： Ichiro Yamamoto

IPC分类号： G07D7/16 ,  G07D7/20 ,  G06K9/00 ,  G06K9/68

CPC分类号： G07D7/20 ,  G07D7/183

摘要： A sheet media identification method works out the primary differentiation of the density of each pixel of a transmission image of a bill (FIG. 5, S21), followed by simply binarizing the differentiation result by comparing it with a predetermined threshold value to extract the contour lines of the bill. A Hough-transform is then applied to the binarized contour lines to extract the contour lines passing through the same point on a Hough-plane as the disconnected elements of a single line, followed by extracting a rectangle surrounded by the straight lines corresponding to the points obtained by the Hough-transform. If the number of dots in the non-overlapping part of the rectangle is not less than a predetermined threshold value, cuts out the non-overlapping part as the image of the bill, followed by comparing the cut-out image with a reference image to define the type of the bill.

摘要翻译： 纸张介质识别方法计算出纸币的发送图像的每个像素的密度的主要区别（图5，S 21），然后通过将微分结果与预定阈值进行比较来简单地二值化分化结果，以提取 轮廓线的帐单。 然后将霍夫变换应用于二值化轮廓线，以提取通过与单线断开的元件在霍夫平面上相同点的轮廓线，随后提取由与点对应的直线包围的矩形 通过霍夫变换获得。 如果矩形的非重叠部分中的点数不小于预定阈值，则将非重叠部分作为纸币的图像切出，然后将切出的图像与参考图像进行比较 定义帐单的类型。

公开(公告)号：US06936901B2

公开(公告)日：2005-08-30

申请号：US10746342

申请日：2003-12-29

申请人： Ichiro Yamamoto

发明人： Ichiro Yamamoto

IPC分类号： H01L21/316 ,  H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L29/51 ,  H01L29/78 ,  H01L29/72

CPC分类号： H01L29/517 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/314 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L28/56 ,  H01L29/513

摘要： A semiconductor device is provided which is capable of improving its reliability by using a material having a high relative dielectric constant as a material for its gate insulating film, by suppressing degradation of an EOT (Equivalent oxide Thickness) and by preventing crystallization of the material having a high relative dielectric constant. The semiconductor device (Field Effect Transistor) has a silicon substrate, a seed layer made up of silicon oxide, a gate insulating film made of amorphous hafnium aliminate and a gate electrode made up of polycrystalline silicon formed the gate insulating film. The gate insulating film is so formed that a hafnium concentration decreases monotonously or step by step, whereas an aluminum concentration increases monotonously or step by step along a direction of a thickness of the gate insulating film from the silicon substrate side toward the gate electrode. In a boundary region between a lower layer side region and an upper layer side region in the gate insulating film, the hafnium and aluminum concentrations change continuously.

摘要翻译： 提供一种半导体器件，其能够通过使用具有高相对介电常数的材料作为其栅极绝缘膜的材料来提高其可靠性，通过抑制EOT（等效氧化物厚度）的劣化，并且通过防止具有 高相对介电常数。 半导体器件（场效应晶体管）具有硅衬底，由氧化硅构成的种子层，由无定形铪合金构成的栅极绝缘膜和由多晶硅构成的栅电极形成栅极绝缘膜。 栅极绝缘膜形成为使得铪浓度单调或逐步降低，而铝浓度沿着栅极绝缘膜的厚度从硅衬底侧朝向栅电极单调或逐步增加。 在栅绝缘膜的下层侧区域和上层侧区域之间的边界区域中，铪和铝的浓度连续变化。

公开(公告)号：US06630393B2

公开(公告)日：2003-10-07

申请号：US09782293

申请日：2001-02-14

申请人： Ichiro Yamamoto

发明人： Ichiro Yamamoto

IPC分类号： H01L2131

CPC分类号： H01L21/02189 ,  C23C16/403 ,  C23C16/405 ,  C23C16/409 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02271 ,  H01L21/28194 ,  H01L21/31691 ,  H01L29/511 ,  H01L29/517

摘要： A method for manufacturing a high dielectric constant insulating film made of a metal oxide on a silicon substrate is provided using a material gas mixture containing an oxidizing agent without forming silicon oxide layer on a silicon substrate. The manufacturing method includes the steps of placing the semiconductor substrate into a reaction chamber; introducing an organic metal material, oxidizing agent, and a material having a reducing action; and forming a high dielectric constant gate insulating film on the semiconductor substrate by a chemical reaction in the reaction chamber.

摘要翻译： 使用含有氧化剂的原料气体混合物，在硅衬底上形成氧化硅层，来制造在硅衬底上由金属氧化物制成的高介电常数绝缘膜的方法。 该制造方法包括以下步骤：将半导体衬底放置在反应室中; 引入有机金属材料，氧化剂和具有还原作用的材料; 以及通过反应室中的化学反应在半导体衬底上形成高介电常数栅极绝缘膜。

公开(公告)号：US06200876B1

公开(公告)日：2001-03-13

申请号：US09310997

申请日：1999-05-13

申请人： Ichiro Yamamoto

发明人： Ichiro Yamamoto

IPC分类号： H01L2120

CPC分类号： H01L28/84

摘要： A method of producing a semiconductor device includes a heat-treating step of heat-treating an HSG'ed capacitor electrode in a dopant gas which does not form a reaction product with silicon. In the heat-treating step, heat treatment is performed in an atmosphere containing the dopant gas of AsH3 in a clean condition such that no oxide film is formed on the surface of each HSG after the HSG is formed. The heat treatment is carried out at a temperature between 550 and 800° C. so that a dopant of arsenic (As) at a high concentration is introduced into the HSG 2a without reducing the size of the HSG 2a by the heat treatment to thereby suppress reduction in capacitance due to depletion. In this condition, when the dopant of As is introduced into the interior of the HSG 2a to form a diffusion region P1, the size of the HSG 2a is not reduced after the diffusion.

摘要翻译： 制造半导体装置的方法包括对不与硅形成反应产物的掺杂气体中的HSG电容电极进行热处理的热处理工序。 在热处理工序中，在干燥条件下，在含有AsH 3的掺杂气体的气氛中进行热处理，使得在形成HSG之后，在各HSG的表面上不形成氧化膜。 热处理在550〜800℃的温度下进行，使得高浓度的砷（As）的掺杂剂通过热处理而不降低HSG 2a的尺寸而被引入HSG 2a中，从而抑制 由于耗尽而导致的电容减小。 在这种情况下，当将As的掺杂剂引入到HSG 2a的内部以形成扩散区域P1时，扩散后HSG 2a的尺寸不会减小。

公开(公告)号：US6040331A

公开(公告)日：2000-03-21

申请号：US11260

申请日：1998-01-30

申请人： Ichiro Yamamoto ,  Manabu Itoh ,  Masato Shimojo ,  Yasunobu Yumiya ,  Takafumi Mukaihira ,  Yasushige Akada

发明人： Ichiro Yamamoto ,  Manabu Itoh ,  Masato Shimojo ,  Yasunobu Yumiya ,  Takafumi Mukaihira ,  Yasushige Akada

IPC分类号： C07D209/90 ,  C07D401/04 ,  C07D491/06 ,  A61K31/40 ,  A61K31/425 ,  C07D403/00 ,  C07D417/00

CPC分类号： C07D401/04 ,  C07D209/90 ,  C07D491/06

摘要： The invention provides novel benzindole derivatives, processes for producing them, as well as a neuroprotective agent, an agent to prevent or treat diseases involving the degeneration, retraction or death of neurons, and an analgesic, each containing the benzindole derivatives as an active ingredient. ##STR1##

摘要翻译： PCT No.PCT / JP97 / 01828 Sec。 371日期1998年1月30日 102（e）1998年1月30日PCT PCT 1997年5月29日PCT公布。 出版物WO97 / 45410 PCT 日期1997年12月4日本发明提供新颖的苯并吲哚衍生物，其制备方法以及神经保护剂，预防或治疗涉及神经元变性，缩回或死亡的疾病的试剂，以及各自含有苯并吲哚衍生物 作为活性成分。

公开(公告)号：US5767011A

公开(公告)日：1998-06-16

申请号：US749081

申请日：1996-11-14

申请人： Chingchi Yao ,  Ichiro Yamamoto ,  Shuji Nomura

发明人： Chingchi Yao ,  Ichiro Yamamoto ,  Shuji Nomura

IPC分类号： G06F17/50 ,  H01L23/528 ,  H01L21/28

CPC分类号： H01L23/5286 ,  G06F17/5077 ,  H01L2924/0002 ,  Y10S257/923

摘要： A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.

摘要翻译： 一种用于通过集成电路制造互连的方法和结果。 该方法包括在高电流流动的区域附近添加更多的电力线80,100,1001和/或增加电力线120的宽度和/或增加电力总线140。 所得到的结构还在高电流流动的区域附近提供更多的金属化。 类似于该方法，所得到的结构可以包括额外的电力线80,100,1001和/或更宽的电力线120和/或电力总线140以增加金属化的量。 还提供了改进的路由技术。 这种路由技术包括提供初始Ucs值，然后在高电流区域附近添加附加线路以减小Ucs值。

公开(公告)号：USD706865S1

公开(公告)日：2014-06-10

申请号：US29417763

申请日：2012-04-09

申请人： Mitsuaki Kumagai ,  Takao Obata ,  Noboru Ishii ,  Toshikazu Minegishi ,  Yoshiaki Kasai ,  Ichiro Yamamoto ,  Atsushi Kobayashi ,  Yoshikazu Kawamoto ,  Yoshihito Kouda ,  Katsutoshi Matsuura ,  Kazuhito Miura ,  Taku Ando ,  Tomohiro Takizawa ,  Yu Kurosawa ,  Yuki Zetsu

设计人： Mitsuaki Kumagai ,  Takao Obata ,  Noboru Ishii ,  Toshikazu Minegishi ,  Yoshiaki Kasai ,  Ichiro Yamamoto ,  Atsushi Kobayashi ,  Yoshikazu Kawamoto ,  Yoshihito Kouda ,  Katsutoshi Matsuura ,  Kazuhito Miura ,  Taku Ando ,  Tomohiro Takizawa ,  Yu Kurosawa ,  Yuki Zetsu

公开(公告)号：US07615500B2

公开(公告)日：2009-11-10

申请号：US11715847

申请日：2007-03-09

申请人： Kensuke Takano ,  Ichiro Yamamoto ,  Koji Watanabe

发明人： Kensuke Takano ,  Ichiro Yamamoto ,  Koji Watanabe

IPC分类号： H01L21/31

CPC分类号： H01L21/02148 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/517

摘要： A method for depositing a film includes: (a) processing a wafer, including forming a high dielectric constant film on a first wafer; and achieving nitridation of the high dielectric constant film formed on the first wafer; and (b) performing coating process including forming a high dielectric constant film on a second wafer; and achieving nitridation of the high dielectric constant film formed on the second wafer. The processing the wafer and the performing the coating process are carried out in the same reaction chamber. The coating process is carried out before the processing the wafer.

摘要翻译： 一种沉积膜的方法包括：（a）处理晶片，包括在第一晶片上形成高介电常数膜; 并且实现在第一晶片上形成的高介电常数膜的氮化; 和（b）进行包括在第二晶片上形成高介电常数膜的涂覆工艺; 并且实现在第二晶片上形成的高介电常数膜的氮化。 在相同的反应室中进行晶片的处理和进行涂覆处理。 涂覆工艺在加工晶片之前进行。

公开(公告)号：US20060214553A1

公开(公告)日：2006-09-28

申请号：US10547211

申请日：2004-02-27

申请人： Yoshiaki Nagara ,  Takanori Murasaki ,  Kenji Mori ,  Ichiro Yamamoto ,  Yoshifumi Kato ,  Shintaro Kawasaki ,  Kazuyoshi Takeuchi

发明人： Yoshiaki Nagara ,  Takanori Murasaki ,  Kenji Mori ,  Ichiro Yamamoto ,  Yoshifumi Kato ,  Shintaro Kawasaki ,  Kazuyoshi Takeuchi

IPC分类号： H01J1/62

CPC分类号： H01L51/5036 ,  H01L51/50 ,  H01L51/5048 ,  H05B33/14

摘要： The present invention provides organic EL devices which have on their anode at least a light-emitting layer, an electron-injecting-transporting layer, and a cathode giving an elongated lifetime, organic EL devices giving a superior whiteness, a higher light-emitting efficiency, and an elongated lifetime compared to conventional ones, and color displays using such organic EL devices. On anode (10), hole-injecting-transporting layer (11), light-emitting layer (12), non-light-emitting layer (13), electron-injecting-transporting layer (14), and cathode (15) in this order are laminated. Otherwise, on an anode, a hole-injecting layer, a hole-transporting layer, a red light-emitting layer, a blue light-emitting layer, an electron-transporting layer, an electron-injecting layer, and a cathode in this order are laminated.

摘要翻译： 本发明提供了在其阳极上至少具有发光层，电子注入传输层和延长寿命的阴极的有机EL器件，具有优异的白度的有机EL器件，更高的发光效率 ，并且与常规的相比具有延长的寿命，以及使用这种有机EL器件的彩色显示器。 在阳极（10），空穴注入传输层（11），发光层（12），非发光层（13），电子注入传输层（14）和阴极（15） 这个顺序是层叠的。 另外，在阳极上，依次是空穴注入层，空穴传输层，红色发光层，蓝色发光层，电子传输层，电子注入层和阴极 层压。

公开(公告)号：US20060038236A1

公开(公告)日：2006-02-23

申请号：US11205141

申请日：2005-08-17

申请人： Ichiro Yamamoto

发明人： Ichiro Yamamoto

IPC分类号： H01L29/94

CPC分类号： H01L29/518 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/78

摘要： A P-type MOSFET 120 includes a semiconductor substrate (N-well 102b); a gate insulating film formed on the semiconductor substrate, composed of a high-dielectric-constant film 108 which contains a silicate compound containing a first element selected from the group consisting of Hf, Zr and any of lanthanoids, together with N; a gate electrode formed on the gate insulating film, and is configured by a polysilicon film 114 containing a P-type impurity; and a blocking oxide film 110 formed between the gate insulating film and the gate electrode, blocking a reaction between the first element and the polysilicon film 114, and having a relative dielectric constant of 8 or above.

摘要翻译： P型MOSFET120包括半导体衬底（N阱102b）; 形成在半导体衬底上的栅极绝缘膜，由含有选自Hf，Zr和任何镧系元素的第一元素的硅酸盐化合物与N的高介电常数膜108组成; 形成在栅极绝缘膜上的栅电极，由包含P型杂质的多晶硅膜114构成; 以及形成在栅极绝缘膜和栅电极之间的阻挡氧化膜110，阻挡第一元件和多晶硅膜114之间的反应，并且具有8或更高的相对介电常数。