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66 条记录 (耗时 0.036 秒)

    Vertical memory devices and methods of manufacturing the same
    41.
    发明授权
    Vertical memory devices and methods of manufacturing the same 有权
    垂直存储器件及其制造方法

    公开(公告)号：US08772857B2

    公开(公告)日：2014-07-08

    申请号：US13221380

    申请日：2011-08-30

    申请人： Byeong-In Choe ,  Jae-Hoon Jang ,  Sun-Il Shim ,  Han-Soo Kim ,  Jin-Man Han

    发明人： Byeong-In Choe ,  Jae-Hoon Jang ,  Sun-Il Shim ,  Han-Soo Kim ,  Jin-Man Han

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11582 ,  H01L29/7926

    摘要： A vertical memory device includes a channel, a ground selection line (GSL), word lines and a string selection line (SSL). The channel extends in a first direction substantially perpendicular to a top surface of a substrate, and a thickness of the channel is different according to height. The GSL, the word lines and the SSL are sequentially formed on a sidewall of the channel in the first direction and spaced apart from each other.

    摘要翻译： 垂直存储器件包括通道，接地选择线（GSL），字线和字符串选择线（SSL）。 通道沿基本上垂直于基板的顶表面的第一方向延伸，并且通道的厚度根据高度而不同。 GSL，字线和SSL顺序地形成在通道的第一方向的侧壁上并且彼此间隔开。

    MULTIPLE-LAYER NON-VOLATILE MEMORY DEVICES, MEMORY SYSTEMS EMPLOYING SUCH DEVICES, AND METHODS OF FABRICATION THEREOF
    43.
    发明申请
    MULTIPLE-LAYER NON-VOLATILE MEMORY DEVICES, MEMORY SYSTEMS EMPLOYING SUCH DEVICES, AND METHODS OF FABRICATION THEREOF 有权
    多层非易失性存储器件，使用这种器件的存储器系统及其制造方法

    公开(公告)号：US20110171787A1

    公开(公告)日：2011-07-14

    申请号：US13069869

    申请日：2011-03-23

    申请人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

    发明人： Jonghyuk Kim ,  Han-Soo Kim ,  YoungSeop Rah ,  Min-sung Song ,  Jang Young Chul ,  Soon-Moon Jung ,  Wonseok Cho

    IPC分类号： H01L21/8246

    CPC分类号： H01L21/82385 ,  H01L21/8221 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823468 ,  H01L23/481 ,  H01L23/485 ,  H01L27/0688 ,  H01L27/11526 ,  H01L27/11551 ,  H01L2224/9202 ,  H01L21/76898

    摘要： In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs.

    摘要翻译： 在多层存储器件中，采用该器件的存储器系统和形成这种器件的方法在第一存储器件层上的第二存储器件层包括包括第二存储单元区域的第二衬底。 第二衬底仅包括第二存储单元区域中的单个阱，第二存储单元区域的单阱包括掺杂有第一类型和第二类型之一杂质的半导体材料。 单阱限定了第二衬底的第二存储单元区域中的有源区。 多个第二电池串被布置在第二有源区域中的第二衬底上。 虽然第二存储单元区域仅包括单个阱，但是在第二层的存储单元的编程或擦除操作期间，需要向第二层的衬底中的单个阱施加高电压，高电压将 不妨碍第一层，第二层或其它层的外围晶体管的操作，因为它们彼此隔离。 结果，第二层的基底可以被制备成具有更薄的轮廓，并且具有更少的加工步骤，导致具有更高密度，更高可靠性和降低制造成本的装置。

    3-dimensional flash memory device, method of fabrication and method of operation
    44.
    发明授权
    3-dimensional flash memory device, method of fabrication and method of operation 失效
    3维闪存器件，制造方法和操作方法

    公开(公告)号：US07960844B2

    公开(公告)日：2011-06-14

    申请号：US12499980

    申请日：2009-07-09

    申请人： Young-Chul Jang ,  Han-Soo Kim ,  Jae-Hun Jeong ,  Soon-Moon Jung

    发明人： Young-Chul Jang ,  Han-Soo Kim ,  Jae-Hun Jeong ,  Soon-Moon Jung

    IPC分类号： H01L23/48

    CPC分类号： H01L27/11578 ,  H01L27/11524 ,  H01L27/11551 ,  H02J2007/0049

    摘要： Disclosed are a flash memory device and method of operation. The flash memory device includes a bottom memory cell array and a top memory cell array disposed over the bottom memory cell array. The bottom memory cell array includes a bottom semiconductor layer, a bottom well, and a plurality of bottom memory cell units. The top memory cell array includes a top semiconductor layer, a top well, and a plurality of top memory cell units. A well bias line is disposed over the top memory cell array and includes a bottom well bias line and a top well bias line, The bottom well bias line is electrically connected to the bottom well, and the top well bias line is electrically connected to the top well.

    摘要翻译： 公开了闪存装置和操作方法。 闪速存储器件包括底部存储单元阵列和设置在底部存储单元阵列上的顶部存储器单元阵列。 底部存储单元阵列包括底部半导体层，底部阱以及多个底部存储单元单元。 顶部存储单元阵列包括顶部半导体层，顶部阱以及多个顶部存储单元。 井顶偏置线设置在顶部存储单元阵列上，并且包括底部阱偏置线和顶部阱偏置线。底部阱偏置线电连接到底部阱，并且顶部阱偏置线电连接到 顶好

    Semiconductor memory device
    47.
    发明申请
    Semiconductor memory device 审中-公开
    半导体存储器件

    公开(公告)号：US20100001337A1

    公开(公告)日：2010-01-07

    申请号：US12456537

    申请日：2009-06-18

    申请人： Han-Soo Kim ,  Jae-Hoon Jang ,  Hoo-Sung Cho

    发明人： Han-Soo Kim ,  Jae-Hoon Jang ,  Hoo-Sung Cho

    IPC分类号： H01L29/792 ,  H01L29/66

    CPC分类号： H01L27/11551 ,  H01L27/0207 ,  H01L27/0688

    摘要： A semiconductor memory device includes: sequentially stacked first and second semiconductor layers; at least one first memory transistor disposed on the first semiconductor layer; and at least one second memory transistor disposed on the second semiconductor layer, wherein a gate electrode of the first memory transistor has a broader width than that of the second memory transistor.

    摘要翻译： 半导体存储器件包括：顺序堆叠的第一和第二半导体层; 设置在所述第一半导体层上的至少一个第一存储晶体管; 以及设置在所述第二半导体层上的至少一个第二存储晶体管，其中所述第一存储晶体管的栅电极具有比所述第二存储晶体管宽的宽度。

    Semiconductor device and method of fabricating a semiconductor device
    49.
    发明授权
    Semiconductor device and method of fabricating a semiconductor device 失效
    半导体装置及其制造方法

    公开(公告)号：US06724052B2

    公开(公告)日：2004-04-20

    申请号：US10194300

    申请日：2002-07-15

    申请人： Kang-Sik Cho ,  Hoo-Seung Cho ,  Gyu-Chul Kim ,  Yong Park ,  Han-Soo Kim

    发明人： Kang-Sik Cho ,  Hoo-Seung Cho ,  Gyu-Chul Kim ,  Yong Park ,  Han-Soo Kim

    IPC分类号： H01L2976

    CPC分类号： H01L21/823443 ,  H01L21/28518 ,  H01L21/823425 ,  H01L29/665 ,  H01L29/66659

    摘要： A semiconductor device includes a substrate of a first conductive type, and a well region of an opposite second conductive type is formed in the substrate. A first impurity region of the first conductive type extends to a first depth within the well region, and a second impurity region of the first conductive type is spaced from the first impurity region to define a channel region therebetween and extends to a second depth within the well region. Preferably, the second depth is greater than the first depth. A gate electrode is located over the channel region, and a silicide layer is formed at a third depth within the first impurity region. The third depth is less than the first depth, and a difference between the first depth and the third depth is less than or equal to a difference at which a leakage current from the silicide layer to the well region is sufficient to electrically bias the well region through the silicide layer.

    摘要翻译： 半导体器件包括第一导电类型的衬底，并且在衬底中形成相对的第二导电类型的阱区。 第一导电类型的第一杂质区域延伸到阱区域内的第一深度，并且第一导电类型的第二杂质区域与第一杂质区域间隔开，以在其间限定沟道区域，并延伸到第 井区。 优选地，第二深度大于第一深度。 栅极电极位于沟道区域的上方，在第一杂质区域内的第三深度处形成硅化物层。 第三深度小于第一深度，第一深度和第三深度之间的差小于或等于从硅化物层到阱区域的漏电流足以使阱区域电偏置的差 通过硅化物层。

    Semiconductor memory device and its method of manufacture
    50.
    发明授权
    Semiconductor memory device and its method of manufacture 失效

    公开(公告)号：US06583486B2

    公开(公告)日：2003-06-24

    申请号：US10068175

    申请日：2002-02-06

    申请人： Han-Soo Kim

    发明人： Han-Soo Kim

    IPC分类号： H01L27095

    CPC分类号： H01L21/761 ,  H01L21/823892

    摘要： A semiconductor memory device comprises a semiconductor substrate having a memory cell region and a periphery circuit region. The memory cell region includes first and second conductivity type wells and an array of memory cell formed on the first and second conductivity type wells. The periphery circuit region comprises a guard ring that is formed at a location next to a second conductivity type well and to surround a side portion of the array of memory cells. The guard ring is formed with a depth different from that of the second conductivity type well.