公开(公告)号：US20050083075A1

公开(公告)日：2005-04-21

申请号：US10689431

申请日：2003-10-20

申请人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

发明人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

IPC分类号： G01R31/26

CPC分类号： G01R31/2648 ,  G01R31/2621 ,  G01R31/2644

摘要： An apparatus for characterizing capacitance and thickness of an insulating layer constructed between a conductive gate and a substrate has at least one test structure formed at a surface of a substrate. Each test structure has a bulk region formed of a semiconductor within the surface. Further the test structure has at least one source region and one drain region within the bulk region. A thin insulating layer is placed above the each source region, each drain region, and the bulk region. A conductive gate is placed above the thin insulating layer. A capacitance-voltage measuring device measures a capacitance value of the test structure, while forcing the bulk region between the source region and the drain region to be floating. An insulating layer thickness calculator determines the thickness of the insulating layer from the capacitance.

摘要翻译： 用于表征在导电栅极和衬底之间构造的绝缘层的电容和厚度的装置具有形成在衬底表面上的至少一个测试结构。 每个测试结构具有由表面内的半导体形成的体区。 此外，测试结构在体区内具有至少一个源极区和一个漏极区。 在每个源极区域，每个漏极区域和主体区域上方放置薄的绝缘层。 导电栅极位于薄绝缘层的上方。 电容电压测量装置测量测试结构的电容值，同时迫使源极区域和漏极区域之间的体区域浮动。 绝缘层厚度计算器根据电容确定绝缘层的厚度。

公开(公告)号：US06246075B1

公开(公告)日：2001-06-12

申请号：US09507883

申请日：2000-02-22

申请人： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

发明人： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

IPC分类号： H01L2358

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photoresist. The structures are formed, either on test wafers or in designated areas of wafers containing integrated circuit chips. One of the test structures is designed primarily to minimize plasma damage so that oxide quality, and defect densities may be measured unhampered by interface traps created by plasma exposure. Other structures provide different antenna-to-oxide area ratios, useful for assessing plasma induced oxide damage and breakdown. The current-voltage characteristics of the MOS capacitors are measured by probing the structures on the wafer, thereby providing timely process monitoring capability.

摘要翻译： 描述了包括用于测量MOSFET栅极绝缘的电气质量的多晶硅板MOS电容器阵列的测试结构的集合。 测试结构还测量在金属蚀刻和光致抗蚀剂的等离子体灰化期间引起的这些栅绝缘体的等离子体损伤。 在测试晶片上或在包含集成电路芯片的晶片的指定区域中形成结构。 其中一个测试结构主要设计为最小化等离子体损伤，从而可以通过等离子体曝光产生的界面陷阱来测量氧化物质量和缺陷密度。 其他结构提供不同的天线到氧化物面积比，可用于评估等离子体诱导的氧化物损伤和击穿。 通过探测晶片上的结构来测量MOS电容器的电流 - 电压特性，从而提供及时的过程监控能力。

公开(公告)号：US6127227A

公开(公告)日：2000-10-03

申请号：US236491

申请日：1999-01-25

申请人： Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/8247

CPC分类号： H01L21/28211 ,  H01L21/28273 ,  H01L29/511

摘要： A method of forming a flash memory cell is disclosed where nitrogen treatment or implantation is employed. Nitrogen introduced into the upper layers of the polysilicon of the floating gate is instrumental in forming an unusually thin layer comprising nitrogen-oxygen-silicon. This N--O--Si layer is formed while growing the bottom oxide layer of the oxide-nitride-oxide, or ONO, the intergate layer between the floating gate and the control gate of the flash memory cell. Nitrogen in the first polysilicon layer provides control for the thickness of the bottom oxide while at the same time suppressing the gradual gate oxidation (GGO) effect in the floating gate. The now augmented ONO composite through the N--O--Si layer provides an enhanced intergate dielectric and hence, a flash memory cell with more precise coupling ratio and better performance.

摘要翻译： 公开了一种形成闪存单元的方法，其中采用氮气处理或植入。 引入浮栅的多晶硅的上层的氮有助于形成包含氮 - 氧 - 硅的异常薄的层。 在生长氧化物 - 氮化物 - 氧化物的底部氧化物层（ONO）的同时，在浮动栅极和闪存单元的控制栅极之间形成栅极层，形成N-O-Si层。 第一多晶硅层中的氮提供对底部氧化物的厚度的控制，同时抑制浮动栅极中的逐渐栅极氧化（GGO）效应。 现在通过N-O-Si层增强的ONO复合材料提供增强的隔间电介质，因此提供具有更精确的耦合比和更好性能的闪存单元。

公开(公告)号：US09245746B2

公开(公告)日：2016-01-26

申请号：US14048971

申请日：2013-10-08

申请人： Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang

发明人： Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/12

CPC分类号： H01L29/205 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/02664 ,  H01L21/30612 ,  H01L29/12 ,  H01L29/2003 ,  H01L29/7845 ,  H01L29/7849

摘要： The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.

摘要翻译： 本发明公开了一种具有异质结的半导体复合膜及其制造方法。 半导体复合膜包括：半导体衬底; 以及半导体外延层，其形成在所述半导体基板上，并且具有彼此相对的第一表面和第二表面，其中所述异质结形成在所述第一表面和所述半导体基板之间，并且其中所述半导体外延层进一步 包括通过从第二表面朝向第一表面蚀刻半导体外延层而形成的至少一个凹部。 该凹槽用于减轻半导体复合膜中的应变。

公开(公告)号：US08729630B1

公开(公告)日：2014-05-20

申请号：US14146512

申请日：2014-01-02

申请人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L29/66

CPC分类号： H01L29/4238 ,  H01L21/28114 ,  H01L21/823425 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

公开(公告)号：US20120187483A1

公开(公告)日：2012-07-26

申请号：US13066622

申请日：2011-04-20

申请人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L29/78 ,  H01L21/8232 ,  H01L21/336

CPC分类号： H01L29/4238 ,  H01L21/28114 ,  H01L21/823425 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

摘要翻译： 本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS设备包括：用于定义设备区域的隔离结构; 具有环形结构的门; 位于环外的排水沟; 以及位于环内的轻掺杂漏极，源极和体电极。 为了增加栅极角落处的次阈值电压，角部完全位于隔离结构上，或者轻掺杂漏极与角分开预定距离。

公开(公告)号：US20090117696A1

公开(公告)日：2009-05-07

申请号：US12318065

申请日：2008-12-22

申请人： Hung-Der Su

发明人： Hung-Der Su

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L27/11558 ,  H01L29/66825

摘要： A fully logic process compatible non-volatile memory cell has a well on a substrate, a pair of source and drain outside the well, a channel between the source and drain, a control gate in the well, and a floating gate having a first portion above the channel, and a second portion above the well. The control gate includes two regions having opposite conductivity types and a third region between the two regions and under the second portion of the floating gate, and thus eliminates the parasitic depletion capacitor in the coupling path of the cell, thereby improving the coupling ratio.

摘要翻译： 完全逻辑工艺兼容的非易失性存储单元在衬底上具有良好的阱，阱外的一对源极和漏极，源极和漏极之间的沟道，阱中的控制栅极以及具有第一部分的浮动栅极 在通道上方，以及井上方的第二部分。 控制栅极包括具有相反导电类型的两个区域和位于两个区域之间的第三区域，并且在浮置栅极的第二部分之下，从而消除了电池耦合路径中的寄生耗尽电容器，从而提高了耦合比。

公开(公告)号：US20090066399A1

公开(公告)日：2009-03-12

申请号：US12230953

申请日：2008-09-09

申请人： An-Tung Chen ,  Li-Wen Fang ,  Hung-Der Su

发明人： An-Tung Chen ,  Li-Wen Fang ,  Hung-Der Su

IPC分类号： H03L5/00

CPC分类号： H03K3/012 ,  H03K3/35613

摘要： A level shift circuit includes an input stage and an output stage coupled to each other by two nodes. The input stage changes the voltages on the nodes according to an input signal, and the output stage determines an output signal according to the voltages on the two nodes. In a transition state, the input stage provides a large current to charge or discharge the first node or the second node so as to quickly change the voltage thereon. In a steady state, the input stage lowers the current so as to reduce power consumption.

摘要翻译： 电平移位电路包括通过两个节点彼此耦合的输入级和输出级。 输入级根据输入信号改变节点上的电压，输出级根据两个节点上的电压来确定输出信号。 在过渡状态下，输入级提供大电流以对第一节点或第二节点进行充电或放电，以便快速地改变其上的电压。 在稳定状态下，输入级降低电流，从而降低功耗。

公开(公告)号：US06747857B1

公开(公告)日：2004-06-08

申请号：US10062706

申请日：2002-02-01

申请人： Jian-Hsing Lee ,  Hung-Der Su ,  Jiaw-Ren Shih

发明人： Jian-Hsing Lee ,  Hung-Der Su ,  Jiaw-Ren Shih

IPC分类号： H02H900

CPC分类号： H03K17/0822 ,  H01L27/0266 ,  H03K17/6872

摘要： A novel device and process is described for an ESD protection device for complimentary cascaded NMOS output circuit strings. The invention consists of a clamping NMOS with gate connected to the input or output pad through a diode and connected to ground through a resistor. The clamping device drain is connected to the signal gate of the active output NMOS and the clamping device source is connected to ground. An ESD event causes the diode to go into breakdown mode and the conduction current across the resistor places a positive voltage on the clamping device gate turning the clamping device on. This clamps the active NMOS signal gate to ground assuring that the output NMOS remains in an off condition during the ESD event. This prevents any damage due to high current flow through the active, or used output inverter string.

摘要翻译： 对于用于互补级联的NMOS输出电路串的ESD保护器件描述了一种新颖的器件和工艺。 本发明包括一个钳位NMOS，其栅极通过二极管连接到输入或输出焊盘，并通过电阻器连接到地。 钳位装置漏极连接到有源输出NMOS的信号栅极，钳位装置源连接到地。 ESD事件导致二极管进入击穿模式，并且电阻两端的导通电流在夹紧装置门上施加正电压，使夹紧装置打开。 这将有源NMOS信号栅极钳位到地，确保在ESD事件期间输出NMOS保持关断状态。 这可以防止由于高电流流过有源或使用的输出逆变器串造成的任何损坏。

公开(公告)号：US06653709B2

公开(公告)日：2003-11-25

申请号：US10213612

申请日：2002-08-07

申请人： Yi-Hsu Wu ,  Hung-Der Su ,  Jian-Hsing Lee ,  Boon-Khim Liew

发明人： Yi-Hsu Wu ,  Hung-Der Su ,  Jian-Hsing Lee ,  Boon-Khim Liew

IPC分类号： H01L2972

CPC分类号： H01L27/092 ,  H01L21/823814 ,  H01L27/0266

摘要： A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground. The fourth NMOS transistor has the gate connected to the voltage supply, the source connected to the third MOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source.