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    Electrochemical fabrication method including elastic joining of structures
    43.
    发明授权
    Electrochemical fabrication method including elastic joining of structures 有权

    公开(公告)号：US09597834B2

    公开(公告)日：2017-03-21

    申请号：US14194214

    申请日：2014-02-28

    Applicant: Microfabrica Inc.

    Inventor： Adam L. Cohen ,  Vacit Arat ,  Michael S. Lockard ,  Dennis R. Smalley

    IPC: C25D5/02 ,  C25D5/48 ,  B29C65/56

    CPC classification number: B29C65/56 ,  B33Y10/00 ,  C25D5/02 ,  Y10T29/49885

    Abstract: Forming multi-layer 3D structures involving the joining of at least two structural elements, at least one of which is formed as a multi-layer 3D structure, wherein the joining occurs via one of: (1) elastic deformation and elastic recovery, (2) relative deformation of an initial portion of at least one element relative to another portion of the at least one element until the at least two elements are in a desired retention position after which the deformation is reduced or eliminated, or (3) moving a retention region of one element into the retention region of the other element, without deformation of either element, along a path including a loading region of the other element and wherein during normal use the first and second elements are configured relative to one another so that the loading region of the second element is not accessible to the retention region of the first element.

    Electrochemical fabrication methods incorporating dielectric materials and/or using dielectric substrates
    44.
    发明授权
    Electrochemical fabrication methods incorporating dielectric materials and/or using dielectric substrates 有权
    电介质材料和/或使用电介质基片的电化学制造方法

    公开(公告)号：US09546431B2

    公开(公告)日：2017-01-17

    申请号：US14185613

    申请日：2014-02-20

    Applicant: Microfabrica Inc.

    Inventor： Adam L. Cohen ,  Michael S. Lockard ,  Kieun Kim ,  Qui T. Le ,  Gang Zhang ,  Uri Frodis ,  Dale S. McPherson ,  Dennis R. Smalley

    IPC: C25D5/02 ,  C25D1/00 ,  C23C18/16 ,  B81C1/00

    CPC classification number: C25D5/022 ,  B81C1/00126 ,  B81C2201/0109 ,  B81C2201/019 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  Y10T156/11 ,  Y10T156/19

    Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations. Other embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material. In some embodiments the dielectric material is a UV-curable photopolymer.

    Abstract translation: 本发明的一些实施例涉及在电介质或部分电介质基底上建立单层或多层结构的技术。 某些实施方案将种子层材料直接沉积到基底材料上，而其它实施例使用中间粘合层材料。 一些实施例使用不同种子层材料和/或用于牺牲和结构导电建筑材料的粘合层材料。 一些实施例将种子层和/或粘合层材料应用于有选择性的方式，而其它实施例以毯子的方式应用材料。 一些实施例通过平面化操作去除外来沉积物（例如沉积到不想要形成层的一部分的区域），而其他实施例通过蚀刻操作去除外来材料。 其它实施方案涉及使用至少一种导电结构材料，至少一种导电牺牲材料和至少一种电介质材料形成的多层中尺度或微结构结构的电化学制造。 在一些实施方案中，电介质材料是可UV固化的光聚合物。

    Counterfeiting Deterrent and Security Devices, Systems, and Methods
    45.
    发明申请
    Counterfeiting Deterrent and Security Devices, Systems, and Methods 有权
    假冒威慑和安全设备，系统和方法

    公开(公告)号：US20160200073A1

    公开(公告)日：2016-07-14

    申请号：US15076490

    申请日：2016-03-21

    Applicant: Microfabrica Inc.

    Inventor： Gregory P. Schmitz ,  Michael S. Lockard ,  Ming-Ting Wu ,  Eric C. Miller ,  Adam L. Cohen

    IPC: B32B15/01 ,  C25D5/48 ,  C25D5/02

    CPC classification number: C25D1/003 ,  B32B15/01 ,  B33Y10/00 ,  B33Y40/00 ,  B33Y70/00 ,  B33Y80/00 ,  C25D1/08 ,  C25D5/022 ,  C25D5/48 ,  C25D7/005

    Abstract: A counterfeiting deterrent device according to one implementation of the disclosure includes a plurality of layers formed by an additive process. Each of the layers may have a thickness of less than 100 microns. At least one of the layers has a series of indentations formed in an outer edge of the layer such that the indentations can be observed to verify that the device originated from a predetermined source. According to another implementation, a counterfeiting deterrent device includes at least one raised layer having outer edges in the shape of a logo. A light source is configured and arranged to shine a light through a slit in a substrate layer of the device and past an intermediate layer to light up the outer edge of the raised layer. The layers of the device are formed by an additive process and have a thickness of less than 100 microns each.

    Abstract translation: 根据本公开的一个实施方式的防伪装置包括通过添加过程形成的多个层。 每个层可以具有小于100微米的厚度。 层中的至少一个具有形成在层的外边缘中的一系列凹痕，使得可以观察到凹痕以验证装置源自预定源。 根据另一个实施方案，一种防伪装置包括至少一个具有标志形状的外边缘的凸起层。 光源被配置和布置成将光照射穿过设备的基底层中的狭缝并且经过中间层以照亮凸起层的外边缘。 装置的层通过添加工艺形成，并且具有小于每个100微米的厚度。

    Batch Methods of Forming Microscale or Millimeter Scale Structures Using Electro Discharge Machining Alone or In Combination with Other Fabrication Methods
    46.
    发明申请
    Batch Methods of Forming Microscale or Millimeter Scale Structures Using Electro Discharge Machining Alone or In Combination with Other Fabrication Methods 审中-公开
    使用单独或与其他制作方法组合的电子放电加工形成微尺度或毫米级结构的批量方法

    公开(公告)号：US20150021299A1

    公开(公告)日：2015-01-22

    申请号：US14333476

    申请日：2014-07-16

    Applicant: Microfabrica Inc.

    Inventor： Heath A. Jensen ,  Uri Frodis ,  Christopher G. Wiita ,  Michael S. Lockard

    IPC: B23H1/04

    CPC classification number: B23H1/04

    Abstract: Embodiments are directed to forming three-dimensional millimeter scale or micro-scale structures from single or multiple sheets or layers of material via electro discharge machining (EDM). In some embodiments, the electrodes are formed by single layer or multi-layer, single material or multi-material deposition processes. In some embodiments single electrodes form a plurality of parts or structures simultaneously. In some embodiments a sacrificial bridging material is used to hold parts together during and after EDM processing.

    Abstract translation: 实施例涉及通过放电加工（EDM）从单个或多个片材或材料层形成三维毫米级或微尺度结构。 在一些实施例中，电极通过单层或多层单材料或多材料沉积工艺形成。 在一些实施例中，单个电极同时形成多个部件或结构。 在一些实施例中，牺牲桥接材料用于在EDM处理期间和之后将部件保持在一起。

    Electrochemical Fabrication Methods Incorporating Dielectric Materials and/or Using Dielectric Substrates
    48.
    发明申请
    Electrochemical Fabrication Methods Incorporating Dielectric Materials and/or Using Dielectric Substrates 有权
    电介质材料和/或使用介质基片的电化学制造方法

    公开(公告)号：US20140209473A1

    公开(公告)日：2014-07-31

    申请号：US14185613

    申请日：2014-02-20

    Applicant: Microfabrica Inc.

    Inventor： Adam L. Cohen ,  Michael S. Lockard ,  Kieun Kim ,  Qui T. Le ,  Gang Zhang ,  Uri Frodis ,  Dale S. McPherson ,  Dennis R. Smalley

    IPC: C25D5/02

    CPC classification number: C25D5/022 ,  B81C1/00126 ,  B81C2201/0109 ,  B81C2201/019 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  Y10T156/11 ,  Y10T156/19

    Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations. Other embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material. In some embodiments the dielectric material is a UV-curable photopolymer.

    Abstract translation: 本发明的一些实施例涉及在电介质或部分电介质基底上建立单层或多层结构的技术。 某些实施方案将种子层材料直接沉积到基底材料上，而其它实施例使用中间粘合层材料。 一些实施例使用不同种子层材料和/或用于牺牲和结构导电建筑材料的粘合层材料。 一些实施例将种子层和/或粘合层材料应用于有选择性的方式，而其它实施例以毯子的方式应用材料。 一些实施例通过平面化操作去除外来沉积物（例如沉积到不想要形成层的一部分的区域），而其他实施例通过蚀刻操作去除外来材料。 其它实施方案涉及使用至少一种导电结构材料，至少一种导电牺牲材料和至少一种电介质材料形成的多层中尺度或微结构结构的电化学制造。 在一些实施方案中，电介质材料是可UV固化的光聚合物。

    Multi-Layer, Multi-Material Micro-Scale and Millimeter-Scale Devices with Enhanced Electrical and/or Mechanical Properties
    49.
    发明申请
    Multi-Layer, Multi-Material Micro-Scale and Millimeter-Scale Devices with Enhanced Electrical and/or Mechanical Properties 有权
    具有增强的电气和/或机械性能的多层，多材料微尺度和毫米级装置

    公开(公告)号：US20140134453A1

    公开(公告)日：2014-05-15

    申请号：US14017535

    申请日：2013-09-04

    Applicant: Microfabrica Inc.

    Inventor： Ming Ting Wu ,  Rulon J. Larsen, III ,  Young Kim ,  Kieun Kim ,  Adam L. Cohen ,  Ananda H. Kumar ,  Michael S. Lockard ,  Dennis R. Smalley

    IPC: B32B15/01

    CPC classification number: G01R1/06761 ,  B32B15/01 ,  Y10T428/12486

    Abstract: Some embodiments of the invention are directed to electrochemical fabrication methods for forming structures or devices (e.g. microprobes for use in die level testing of semiconductor devices) from a core material and a shell or coating material that (1) partially coats the surface of the structure, (2) completely coats the surface of the structure, and/or (3) completely coats the surface of structural material of each layer from which the structure is formed including interlayer regions. These embodiments incorporate both the core material and the shell material into the structure as each layer is formed along with a sacrificial material that is removed after formation of all layers of the structure. In some embodiments the core material may be a material that would be removed with sacrificial material if it were accessible by an etchant during removal of the sacrificial material.

    Abstract translation: 本发明的一些实施方案涉及用于从核心材料和壳或涂层材料形成结构或器件（例如用于半导体器件的晶片级测试的微探针）的电化学制造方法，（1）部分地涂覆结构的表面 ，（2）完全涂覆结构的表面，和/或（3）完全涂覆包含中间层区域的结构形成的各层结构材料的表面。 这些实施例将芯材料和壳体材料结合到结构中，因为每个层与形成所述结构的所有层之后被去除的牺牲材料一起形成。 在一些实施例中，芯材料可以是如果在去除牺牲材料期间可通过蚀刻剂使用牺牲材料将其去除的材料。

    Method of Forming Electrically Isolated Structures Using Thin Dielectric Coatings
    50.
    发明申请
    Method of Forming Electrically Isolated Structures Using Thin Dielectric Coatings 审中-公开
    使用薄介电涂层形成电隔离结构的方法

    公开(公告)号：US20140008235A1

    公开(公告)日：2014-01-09

    申请号：US13657375

    申请日：2012-10-22

    Applicant: Microfabrica Inc.

    Inventor： Dennis R. Smalley ,  Adam L. Cohen ,  Ananda H. Kumar ,  Michael S. Lockard

    IPC: C25D5/02

    CPC classification number: A61N1/00 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  C25D1/20 ,  C25D5/022 ,  G01R1/0483 ,  G01R1/06716 ,  G01R1/07357 ,  G01R31/2886 ,  H05K3/467 ,  H05K3/4682

    Abstract: Electrochemical fabrication processes and apparatus for producing multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers including operations for providing coatings of dielectric material that isolate at least portions of a first conductive material from (1) other portions of the first conductive material, (2) a second conductive material, or (3) another dielectric material, and wherein the thickness of the dielectric coatings are thin compared to the thicknesses of the layers used in forming the structures. In some preferred embodiments, portions of each individual layer are encapsulated by dielectric material while in other embodiments only boundaries between distinct regions of materials are isolated from one another by dielectric barriers.

    Abstract translation: 用于生产多层结构的电化学制造方法和装置，其中每个层包括至少两种材料的沉积，并且其中形成至少一些层，包括用于提供将第一导电材料的至少一部分与 （1）第一导电材料的其它部分，（2）第二导电材料或（3）另一种电介质材料，并且其中电介质涂层的厚度与用于形成结构的层的厚度相比较薄。 在一些优选实施例中，每个单独层的部分被电介质材料包封，而在其它实施例中，材料的不同区域之间的边界通过电介质屏障彼此隔离。

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