公开(公告)号：US20250054898A1

公开(公告)日：2025-02-13

申请号：US18789266

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Akshay N. Singh

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor device, including a lower semiconductor die, one or more upper semiconductor dies disposed over the lower semiconductor die, a non-conductive fillet material disposed between adjacent semiconductor dies of the lower semiconductor die and the one or more upper semiconductor dies, the non-conductive fillet material having edge regions that squeeze out from space between adjacent semiconductor dies, a dielectric layer disposed on a backside of the lower semiconductor die and under the one or more upper semiconductor dies, a buffer layer disposed above the dielectric layer and in contact to at least one edge region of the non-conductive fillet material, and an encapsulant material disposed on sidewalls and top surface of the semiconductor device, the encapsulant material encapsulating the lower semiconductor die and the one or more upper semiconductor dies.

公开(公告)号：US20240379503A1

公开(公告)日：2024-11-14

申请号：US18780303

申请日：2024-07-22

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

公开(公告)号：US12080678B2

公开(公告)日：2024-09-03

申请号：US17881572

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Benjamin L. McClain ,  Mark E. Tuttle

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/75 ,  H01L23/481 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/75317 ,  H01L2224/81203 ,  H01L2224/95091

Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

公开(公告)号：US20240063068A1

公开(公告)日：2024-02-22

申请号：US17892036

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Bret K. Street ,  Terrence B. McDaniel ,  Jaekyu Song

IPC: H01L23/13 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/13 ,  H01L25/0652 ,  H01L25/50 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5382 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/73

Abstract: A semiconductor device assembly comprises a package substrate including (i) an upper surface having a plurality of internal contacts, (ii) a lower surface having a plurality of external contacts coupled to the plurality of internal contacts, and (iii) a cavity extending into the package substrate. The assembly further comprises a stack of first semiconductor devices disposed in the cavity, an uppermost first semiconductor device of the stack having a plurality of stack contacts, and an interposer including (i) a bottom surface having a first plurality of lower contacts coupled to the plurality of stack contacts and a second plurality of lower contacts coupled to the plurality of internal contacts, and (ii) a top surface having a plurality of upper contacts coupled to the first and second pluralities of lower contacts. The assembly further comprises a second semiconductor device including a plurality of die contacts coupled to the plurality of upper contacts.

公开(公告)号：US20230343673A1

公开(公告)日：2023-10-26

申请号：US17728625

申请日：2022-04-25

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Amy R. Griffin

IPC: H01L23/373 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3737 ,  H01L23/3735 ,  H01L23/3675 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L24/96 ,  H01L24/97 ,  H01L24/32 ,  H01L2224/32145 ,  H01L2924/1436 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2224/08221 ,  H01L2224/80896

Abstract: A semiconductor device assembly that includes carbon nanofibers (CNFs) for heat dissipation has a CNF layer. Molding compound encapsulates the CNF layer to form an encapsulated CNF layer. The molding compound extends between individual adjacent CNFs within the encapsulated CNF layer, and upper edges of at least a portion of individual CNFs within the encapsulated CNF layer are exposed along an upper surface of the encapsulated CNF layer. The upper surface of the CNF layer is removably attached to a bottom surface of a carrier wafer.

公开(公告)号：US20230343672A1

公开(公告)日：2023-10-26

申请号：US17728586

申请日：2022-04-25

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Amy R. Griffin

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/373 ,  H01L23/367

CPC classification number: H01L23/3737 ,  H01L23/3675 ,  H01L23/3735 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L24/32 ,  H01L2224/08221 ,  H01L2224/32145 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2924/1436

Abstract: A semiconductor device assembly that includes carbon nanofibers (CNFs) for heat dissipation has a CNF layer. Molding compound encapsulates the CNF layer to form an encapsulated CNF layer. The molding compound extends between individual adjacent CNFs within the encapsulated CNF layer, and upper edges of at least a portion of individual CNFs within the encapsulated CNF layer are exposed along an upper surface of the encapsulated CNF layer. The upper surface of the CNF layer is removably attached to a bottom surface of a carrier wafer.

公开(公告)号：US20230260877A1

公开(公告)日：2023-08-17

申请号：US17670393

申请日：2022-02-11

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L24/16 ,  H01L25/0657 ,  H01L21/76898 ,  H01L2225/06541

Abstract: A semiconductor device having monolithic conductive cylinders, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, and a top dielectric layer. The conductive pad may be at a first surface of the semiconductor substrate. The opening may be ring-shaped and extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the top dielectric layer may cover the second surface and may fill the opening. A second ring-shaped opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

公开(公告)号：US11410973B2

公开(公告)日：2022-08-09

申请号：US16939756

申请日：2020-07-27

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Randon K. Richards ,  Aparna U. Limaye ,  Dong Soon Lim ,  Chan H. Yoo ,  Bret K. Street ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L21/78 ,  H01L21/66 ,  H01L25/00 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/48

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

公开(公告)号：US11410963B2

公开(公告)日：2022-08-09

申请号：US17099655

申请日：2020-11-16

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Benjamin L. McClain ,  Mark E. Tuttle

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/48

Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

公开(公告)号：US20220102308A1

公开(公告)日：2022-03-31

申请号：US17035579

申请日：2020-09-28

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Bret K. Street

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00

Abstract: Systems and methods for semiconductor devices having a substrate with bond pads, a die pair in a stacked configuration above the bond pads and having a first die having an oxide layer, a second die having an oxide layer attached to the first oxide layer, and conductive bonds electrically coupling the dies. Interconnects extend between the bond pads and the die pair, electrically coupling die pair to the substrate. The device may include a second die pair electrically coupled to: (1) the first die pair with secondary interconnects; and (2) the substrate with through-silicon vias extending through the first die pair. The top die of a die pair may be a thick die for use at the top of a pair stack. Pairs may be created by matching dies of a first silicon wafer to dies of a second silicon wafer, combination bonding the wafers, and dicing the die pairs.