公开(公告)号：US20180061460A1

公开(公告)日：2018-03-01

申请号：US15667234

申请日：2017-08-02

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C7/06

CPC classification number: G11C7/065 ,  G11C7/062 ,  G11C7/067 ,  G11C2207/063 ,  H01L21/8221 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10897 ,  H01L29/66666

Abstract: A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.

公开(公告)号：US20170358338A1

公开(公告)日：2017-12-14

申请号：US15181188

申请日：2016-06-13

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/22 ,  G11C11/4099 ,  G11C7/14

CPC classification number: G11C11/2273 ,  G11C7/14 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2275 ,  G11C11/4099 ,  G11C2211/5634

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.

公开(公告)号：US09159392B2

公开(公告)日：2015-10-13

申请号：US14254433

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Tae Kim ,  Howard C. Kirsch ,  Charles L. Ingalls ,  Shigeki Tomishima ,  K. Shawn Smith

IPC: G11C5/02 ,  G11C8/08 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  G11C8/14 ,  H01L27/118

CPC classification number: G11C8/08 ,  G11C5/025 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

Abstract: Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed.

Abstract translation: 存储器子系统和方法，例如涉及形成在第一类型的半导体材料上的存储单元阵列的那些，例如p型衬底。 在至少一个这样的子系统中，用于选择性地访问阵列内的单元的所有晶体管都是第二类型的晶体管，例如n型晶体管。 本地字线驱动器耦合到延伸穿过阵列的相应字线。 每个本地字线驱动器包括至少一个晶体管。 然而，本地字线驱动器中的所有晶体管都是第二类。 第二种类型的半导体材料的阱也形成在第一类型的材料中，并且使用该阱形成多个全局字线驱动器。 公开了其他子系统和方法。

公开(公告)号：US20150117124A1

公开(公告)日：2015-04-30

申请号：US14068940

申请日：2013-10-31

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls ,  Howard Kirsch ,  Tae H. Kim

IPC: G11C7/08 ,  G11C7/12

CPC classification number: G11C7/08 ,  G11C7/12

Abstract: Some embodiments include apparatuses and methods having a first data line, a second data line, a first transistor, a sense amplifier, and a circuit. The first transistor can operate to couple the first data line to a first node during a first stage of an operation of obtaining information from a memory cell associated with the first data line. The second transistor can operate to couple the second data line to a second node during the first stage. The circuit can operate to apply a first signal to a gate of the first transistor during the operation and to apply a second signal to a gate of the second transistor during the operation. The sense amplifier can operate to perform a sense function on the first and second data lines during a second stage of the operation. Additional apparatus and methods are described.

Abstract translation: 一些实施例包括具有第一数据线，第二数据线，第一晶体管，读出放大器和电路的装置和方法。 在从与第一数据线相关联的存储器单元获得信息的操作的第一阶段期间，第一晶体管可以操作以将第一数据线耦合到第一节点。 第二晶体管可以在第一阶段期间将第二数据线耦合到第二节点。 电路可操作以在操作期间将第一信号施加到第一晶体管的栅极，并且在操作期间将第二信号施加到第二晶体管的栅极。 感测放大器可以在操作的第二阶段期间操作以在第一和第二数据线上执行感测功能。 描述附加的装置和方法。

公开(公告)号：US12158826B2

公开(公告)日：2024-12-03

申请号：US17853321

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner ,  Charles L. Ingalls

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/20 ,  G11C11/22 ,  G11C29/12 ,  G11C29/36 ,  G11C29/44 ,  G11C29/52 ,  G06F11/10 ,  G11C29/42

Abstract: Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.

公开(公告)号：US20240203482A1

公开(公告)日：2024-06-20

申请号：US18494463

申请日：2023-10-25

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Charles L. Ingalls ,  Shizhong Mei ,  Luoqi Li

IPC: G11C11/4091 ,  G11C11/4074

CPC classification number: G11C11/4091 ,  G11C11/4074

Abstract: A memory device may include multiple memory cells configured to store data. The memory device may also include multiple digit lines that carry data to and from a respective memory cell. The memory device may include multiple sense amplifiers each selectively coupled to respective digit lines and including first and second transistors and first and second gut nodes coupled to the first and second transistors, respectively. Each sense amplifier may amplify a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based on respective charges the digit lines, where a gain of the amplification is based on a negative voltage supplied to the sense amplifier and/or negative digit line write back operations.

公开(公告)号：US11967362B2

公开(公告)日：2024-04-23

申请号：US17829737

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Christopher K. Morzano ,  Christopher J. Kawamura ,  Charles L. Ingalls

IPC: G11C16/04 ,  G11C11/4091

CPC classification number: G11C11/4091

Abstract: A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

公开(公告)号：US20230395130A1

公开(公告)日：2023-12-07

申请号：US17829737

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Huy T. Vo ,  Christopher K. Morzano ,  Christopher J. Kawamura ,  Charles L. Ingalls

IPC: G11C11/4091

CPC classification number: G11C11/4091

Abstract: A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

公开(公告)号：US11636890B2

公开(公告)日：2023-04-25

申请号：US17370515

申请日：2021-07-08

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C11/00 ,  G11C11/22

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

公开(公告)号：US11232829B2

公开(公告)日：2022-01-25

申请号：US16814863

申请日：2020-03-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toby D. Robbs ,  Charles L. Ingalls

IPC: G11C11/4091 ,  H01L27/108 ,  G11C11/4097

Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.