公开(公告)号：US20250004962A1

公开(公告)日：2025-01-02

申请号：US18829713

申请日：2024-09-10

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Leonid Minz ,  Yoav Weinberg ,  Ali Feiz Zarrin Ghalam ,  Luigi Pilolli

IPC: G06F13/30 ,  G06F13/16

Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data transfer across an interface bus to be suspended by toggling a logical level of a control pin from a first level that activates the data transfer to a second level that suspends the data transfer, and causing the data transfer to resume by toggling the logical level of the control pin from the second level to the first level.

公开(公告)号：US20240395338A1

公开(公告)日：2024-11-28

申请号：US18790480

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Violante Moschiano ,  Jeffrey S. McNeil ,  James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat

IPC: G11C16/30 ,  G11C16/10 ,  G11C16/26

Abstract: Processing logic in a memory device receives a calibration scan command associated with the memory device. In response to the calibration scan command, execution of a set of read operations at a plurality of read voltage levels on the memory device is caused. In response to the calibration scan command, a set of bit counts is identified, where each bit count of the set of bit counts corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels. Based on the bit count corresponding to each bin of the set of bins, a bin having a lowest bit count is identified.

公开(公告)号：US20240379178A1

公开(公告)日：2024-11-14

申请号：US18780167

申请日：2024-07-22

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Tomoko Ogura Iwasaki

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: Control logic in a memory device identifies a set of memory cells in a block of a memory array, wherein the set of memory cells comprises two or more memory cells programmed during a program phase of a program operation and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a program verify phase of the program operation and performs concurrent sensing operations on the set of memory cells to determine whether each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.

公开(公告)号：US20240312525A1

公开(公告)日：2024-09-19

申请号：US18605169

申请日：2024-03-14

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Tomoko Ogura Iwasaki ,  Alessio Urbani ,  Justin Bates

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/08

Abstract: A request to execute a programming operation to program multiple sub-blocks including a first sub-block and a second sub-block of a memory device is identified. A first drive operation is executed to load first data into a first select gate drain (SGD) associated with the first sub-block. Following completion of the first drive operation, a second drive operation is executed to load second data into a second SGD associated with the second sub-block. Following completion of the second drive operation, a third drive operation is executed to re-load the first data into the first SGD.

公开(公告)号：US20240311307A1

公开(公告)日：2024-09-19

申请号：US18671846

申请日：2024-05-22

Applicant: Micron Technology, Inc.

Inventor： Sundararajan Sankaranarayanan ,  Eric N. Lee

IPC: G06F12/084 ,  G06F3/06 ,  G06F12/0882 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

CPC classification number: G06F12/084 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0882 ,  G11C16/24 ,  G11C16/26 ,  G06F2212/1024 ,  G06F2212/222 ,  G11C16/0483

Abstract: A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.

公开(公告)号：US12073895B2

公开(公告)日：2024-08-27

申请号：US17683153

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Tomoko Ogura Iwasaki

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: Control logic in a memory device identifies a set of memory cells in a block of a memory array, wherein the set of memory cells comprises two or more memory cells programmed during a program phase of a program operation and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a program verify phase of the program operation and performs concurrent sensing operations on the set of memory cells to determine whether each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.

公开(公告)号：US12019550B2

公开(公告)日：2024-06-25

申请号：US17547818

申请日：2021-12-10

Applicant: Micron Technology, Inc.

Inventor： Sundararajan Sankaranarayanan ,  Eric N. Lee

IPC: G06F12/084 ,  G06F3/06 ,  G06F12/0882 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

CPC classification number: G06F12/084 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0882 ,  G11C16/24 ,  G11C16/26 ,  G06F2212/1024 ,  G06F2212/222 ,  G11C16/0483

Abstract: A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.

公开(公告)号：US20240185926A1

公开(公告)日：2024-06-06

申请号：US18517903

申请日：2023-11-22

Applicant: Micron Technology, Inc.

Inventor： Huai-Yuan Tseng ,  Kishore Kumar Mucherla ,  William Charles Filipiak ,  Eric N. Lee ,  Andrew Bicksler ,  Ugo Russo ,  Niccolo' Righetti ,  Christian Caillat ,  Akira Goda ,  Ting Luo ,  Antonino Pollio

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/16 ,  G11C16/3404

Abstract: A variety of applications can include one or more memory devices having user data preloaded for the application prior to reflowing the memory devices on the system platform of the application. A touch-up data refresh method can be implemented to gain read window budget and to improve retention slope to protect the preload content to tolerate reflow to the system platform. Techniques for data preload can include programming preload data into targeted blocks until the targeted blocks are programmed with the preload data and re-programming the preload data over the programmed preload data in the targeted blocks in a same set of memory cells, without an erase between programming and re-programming the preload data. Variations of such techniques can be used to prepare a memory device with preload data followed by performing a reflow of the memory device to a structure for an application to which the memory device is implemented.

公开(公告)号：US11972135B2

公开(公告)日：2024-04-30

申请号：US17590650

申请日：2022-02-01

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Dheeraj Srinivasan

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory system includes multiple dice having multiple planes. A processing device is coupled to the dice and performs controller operations including receiving a status indicator signal comprising a pulse that is asserted by one or more planes of the multiple dice. In response to receiving the pulse, the processing device performs at least one of: a first status check of dice operations being performed by the multiple dice at an expiration of a polling delay period; or a second status check of the dice operations in response to detecting the pulse being deasserted. The processing device terminates performances of status checks while the status indicator signal remains deasserted.

公开(公告)号：US20240087651A1

公开(公告)日：2024-03-14

申请号：US17941831

申请日：2022-09-09

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Huai-Yuan Tseng ,  Akira Goda ,  Dung V. Nguyen ,  Giovanni Maria Paolucci ,  James Fitzpatrick ,  Eric N. Lee ,  Dave Scott Ebsen ,  Tomoharu Tanaka

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C16/102 ,  G11C16/26 ,  G11C16/32

Abstract: Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.