公开(公告)号：US10223263B2

公开(公告)日：2019-03-05

申请号：US15857435

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Luca Porzio ,  Erminio Di Martino ,  Giacomo Bernardi ,  Domenico Monteleone ,  Stefano Zanardi ,  Chee Weng Tan ,  Sebastien LeMarie ,  Andre Klindworth

IPC: G06F12/08 ,  G06F13/16 ,  G06F13/00 ,  G06F12/0804 ,  G06F12/0891

Abstract: Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

公开(公告)号：US10163472B2

公开(公告)日：2018-12-25

申请号：US15643361

申请日：2017-07-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio

IPC: G11C7/22 ,  G06F13/16 ,  G11C7/10

Abstract: Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation.

公开(公告)号：US10067890B2

公开(公告)日：2018-09-04

申请号：US15667358

申请日：2017-08-02

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F13/16 ,  G11C7/10

Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first information during a variable latency period indicating the memory is not available to perform a command, wherein the first information is indicative of a remaining length of the variable latency period, the remaining length is one of a relatively short, normal, or long period of time, the memory configured to provide second information in response to receiving the command after the latency period.

公开(公告)号：US20170329534A1

公开(公告)日：2017-11-16

申请号：US15667358

申请日：2017-08-02

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F3/06

CPC classification number: G06F13/1689 ,  G06F13/161 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/22 ,  G11C8/06 ,  G11C2207/2209 ,  G11C2207/2272 ,  G11C2207/229

Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first information during a variable latency period indicating the memory is not available to perform a command, wherein the first information is indicative of a remaining length of the variable latency period, the remaining length is one of a relatively short, normal, or long period of time, the memory configured to provide second information in response to receiving the command after the latency period.

公开(公告)号：US09740485B2

公开(公告)日：2017-08-22

申请号：US13840929

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio ,  Chee Weng Tan ,  Sebastien Lemarie ,  Andre Klindworth

IPC: G11C7/10 ,  G11C7/22 ,  G11C13/00 ,  G06F13/16 ,  G06F9/30

CPC classification number: G06F9/30047 ,  G06F13/161 ,  G06F13/1689 ,  G11C7/1063 ,  G11C7/22 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2207/2272

Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.

公开(公告)号：US20170083263A1

公开(公告)日：2017-03-23

申请号：US15367631

申请日：2016-12-02

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Luca Porzio ,  Erminio Di Martino ,  Giacomo Bernardi ,  Domenico Monteleone ,  Stefano Zanardi

IPC: G06F3/06 ,  G06F12/0891 ,  G06F12/0804

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0804 ,  G06F12/0891 ,  G06F2212/7203

Abstract: Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit. The buffer may be coupled to the array and configured to store data. The memory control unit may be coupled to the array and the buffer. The memory control unit may be configured to cause the buffer to store the data responsive, at least in part, to a first write command and may further be configured to cause the buffer to store the data in the array responsive, at least in part, to a flush command. The memory control unit may further be configured to interrupt the flush command to prepare for a read command or a second write command and resume the flush command once the read command or the second write command is performed.

公开(公告)号：US09563565B2

公开(公告)日：2017-02-07

申请号：US13967250

申请日：2013-08-14

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Luca Porzio ,  Erminio Di Martino ,  Giacomo Bernardi ,  Domenico Monteleone ,  Stefano Zanardi

IPC: G06F12/08

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0804 ,  G06F12/0891 ,  G06F2212/7203

Abstract: Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit. The buffer may be coupled to the array and configured to store data. The data may include data intended to be stored in the storage area. The memory control unit may be coupled to the array and the buffer. The memory control unit may be configured to cause the buffer to store the data responsive, at least in part, to a write command and may further be configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

Abstract translation: 本文公开了用于从缓冲器提供数据的装置和方法。 示例性装置可以包括阵列，缓冲器和存储器控制单元。 缓冲器可以耦合到阵列并被配置为存储数据。 数据可以包括要存储在存储区域中的数据。 存储器控制单元可以耦合到阵列和缓冲器。 存储器控制单元可以被配置为使得缓冲器至少部分地响应于写入命令来存储数据，并且还可以被配置为使得缓冲器将要存储在存储区域中的数据存储在存储器 阵列的区域至少部分响应于冲洗命令。

公开(公告)号：US09224440B2

公开(公告)日：2015-12-29

申请号：US14472003

申请日：2014-08-28

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Graziano Mirichigni

IPC: G06F12/00 ,  G11C7/10 ,  G06F12/06 ,  G11C16/10 ,  G11C16/32

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1015 ,  G11C7/1078 ,  G11C7/1084 ,  G11C16/102 ,  G11C16/32 ,  Y02D10/13

Abstract: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command.

Abstract translation: 非易失性存储器件包括：第一缓冲寄存器，用于接收和存储要存储到经由存储器总线提供的存储器件中的数据。 命令窗口可激活以插入其自身以访问第一缓冲元件和存储器矩阵之间的存储器矩阵。 命令窗口包括第二缓冲器元件，其存储存储在存储器或存储到一组存储器元件中的数据。 在通过接收第一命令开始的数据写入操作的第一阶段期间，第一数据传送装置执行将存储在第二缓冲寄存器中的数据的第一传送到第一缓冲寄存器。 第二数据传送装置接收由存储器总线提供的数据，并且在通过接收第二命令开始的数据写入操作的第二阶段期间，基于接收的数据修改存储在第一缓冲寄存器中的数据。 第一传送装置在数据写入操作的第三阶段期间执行将存储在第一缓冲寄存器中的修改数据的第二传送到第二缓冲寄存器。 响应于与第二命令一起接收由存储器总线接收的信号执行第二传送。

公开(公告)号：US20150348599A1

公开(公告)日：2015-12-03

申请号：US14288618

申请日：2014-05-28

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Corrado Villa

IPC: G11C5/14

CPC classification number: G11C5/144 ,  G06F13/1668 ,  G11C5/14 ,  G11C5/142 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/30

Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

Abstract translation: 本公开包括用于向存储器提供功率可用性信息的装置和方法。 许多实施例包括存储器和控制器。 控制器被配置为向存储器提供功率和功率可用性信息，并且存储器被配置为至少部分地基于功率可用性信息来确定是否调整其操作。

公开(公告)号：US20150347038A1

公开(公告)日：2015-12-03

申请号：US14288663

申请日：2014-05-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Domenico Monteleone ,  Giacomo Bernardi ,  Luca Porzio ,  Graziano Mirichigni ,  Stefano Zanardi ,  Erminio Di Martino

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0616 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/7211

Abstract: Apparatuses and methods for commands to perform wear leveling operations are described herein. An example apparatus may include a memory configured to receive a wear leveling command and to perform a wear leveling operation responsive to the wear leveling command. The memory may further be configured to recommend a wear leveling command be provided to the memory responsive to a global write count exceeding a threshold. The global write count may be indicative of a number of write operations performed by the memory since the memory performed a wear leveling operation.

Abstract translation: 本文描述了用于执行磨损均衡操作的命令的装置和方法。 示例性装置可以包括被配置为接收磨损均衡指令并且响应于磨损均衡指令执行磨损均衡操作的存储器。 存储器还可以被配置为响应于超过阈值的全局写入数量来推荐向存储器提供损耗均衡命令。 全局写入计数可以指示存储器执行的写入操作的数量，因为存储器执行了磨损均衡操作。