公开(公告)号：US10446218B2

公开(公告)日：2019-10-15

申请号：US16273598

申请日：2019-02-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  John D. Porter

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4091 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4094 ,  G11C8/06

Abstract: Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal blocks, clock blocking circuits, data input blocks, driver circuits, and data receiver circuits.

公开(公告)号：US10411707B1

公开(公告)日：2019-09-10

申请号：US16051117

申请日：2018-07-31

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee

IPC: H03K19/0185 ,  H03F3/45

Abstract: An input buffer circuit may include a first switch that may couple a first voltage source to an output line based on an enable signal, such that the enable signal is configured to cause the input buffer circuit to operate. The input buffer circuit may also include a first set of switches that may couple the first voltage source to the output line based on the enable signal and an input signal, wherein the first switch and the first set of switches may couple the first voltage source to the output line in response to the input signal being greater than an input reference signal. The input buffer circuit may also include a switch that may couple a second voltage source to the output line in response to the input signal being less than the input reference signal.

公开(公告)号：US20190172519A1

公开(公告)日：2019-06-06

申请号：US16273598

申请日：2019-02-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  John D. Porter

IPC: G11C11/4076 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/06 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/2227 ,  G11C2207/2272

Abstract: Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal blocks, clock blocking circuits, data input blocks, driver circuits, and data receiver circuits.

公开(公告)号：US10311941B1

公开(公告)日：2019-06-04

申请号：US15950041

申请日：2018-04-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee

IPC: H03F1/02 ,  G11C11/40 ,  G11C11/4096 ,  H03F3/45 ,  H03F3/195

Abstract: Apparatuses and methods for input signal receiver circuits are disclosed. An example apparatus includes an amplifier stage configured to receive a reference voltage and an input signal. The amplifier stage is configured to provide in a first mode a first output having a complementary logic level to the input signal and a second output having a same logic level to the input signal and is further configured to provide in a second mode the first output unrelated to the input signal and the second output having a same logic level to the input signal. The example apparatus further includes a pull-up circuit and a pull-down circuit. The pull-up circuit is configured to provide a high logic level voltage to a common node when activated by the first output. The pull-down circuit is configured to provide a low logic level voltage to the common node when activated by the second output.

公开(公告)号：US10210918B2

公开(公告)日：2019-02-19

申请号：US15445935

申请日：2017-02-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G11C8/18 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076

Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.

公开(公告)号：US20190027197A1

公开(公告)日：2019-01-24

申请号：US16138517

申请日：2018-09-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Jongtae Kwak ,  Suryanarayana Tatapudi

IPC: G11C7/00 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4076 ,  G06F1/12 ,  G11C19/00 ,  G11C7/10 ,  G11C11/408 ,  G11C7/22

Abstract: In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent mad commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.

公开(公告)号：US12300300B2

公开(公告)日：2025-05-13

申请号：US17660199

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon ,  Yang Lu ,  Kang-Yong Kim ,  Mark Kalei Hadrick ,  Hyun Yoo Lee

IPC: G11C11/408 ,  G11C11/406 ,  G11C11/4076

Abstract: Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

公开(公告)号：US20250111872A1

公开(公告)日：2025-04-03

申请号：US18747740

申请日：2024-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wonjun Choi ,  Hyun Yoo Lee

IPC: G11C11/406

Abstract: Apparatuses, systems, and methods for refresh rate register adjustment based on a targeted refresh queue. A memory includes a temperature sensor which measures a temperature of the memory. The memory also includes a targeted refresh queue which stores identified aggressor addresses. A value of a refresh rate register is set based on both the measured temperature and the number of addresses in the queue. A controller of the memory reads the value of the refresh rate register and provides a refresh signal with timing based on the refresh rate register. In some embodiments, a ratio of targeted and normal refresh operations is adjusted based on how many addresses are in the targeted refresh queue.

公开(公告)号：US12235783B2

公开(公告)日：2025-02-25

申请号：US17823415

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Francesco Douglas Verna-Ketel ,  Hyun Yoo Lee ,  Smruti Subhash Jhaveri ,  John Christopher Sancon ,  Yang Lu ,  Kang-Yong Kim

IPC: G06F13/40 ,  G06F13/16

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice over a bus to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, the controller may attempt to train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine the bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

公开(公告)号：US20240323062A1

公开(公告)日：2024-09-26

申请号：US18734721

申请日：2024-06-05

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC: H04L25/03 ,  H04L25/49

CPC classification number: H04L25/03057 ,  H04L25/4917

Abstract: Described apparatuses and methods are directed to equalization with pulse-amplitude modulation (PAM) signaling. As bus frequencies have increased, the time for correctly transitioning between voltage levels has decreased, which can lead to errors. Symbol decoding reliability can be improved with equalization, like with decision-feedback equalization (DFE). DFE, however, can be expensive for chip area and power usage. Therefore, instead of applying DFE to all voltage level determination paths in a receiver, DFE can be applied to a subset of such determination paths. With PAM4 signaling, for example, a DFE circuit can be coupled between an output and an input of a middle slicer. In some cases, symbol detection reliability can be maintained even with fewer DFE circuits by compressing a middle eye of the PAM4 signal. The other two eyes thus have additional headroom for expansion. Encoding schemes, impedance terminations, or reference voltage levels can be tailored accordingly.