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    Neural network in a memory device
    41.
    发明授权
    Neural network in a memory device 有权
    神经网络在存储器中

    公开(公告)号：US09430735B1

    公开(公告)日：2016-08-30

    申请号：US13774553

    申请日：2013-02-22

    Applicant: Micron Technology, Inc.

    Inventor： Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis

    IPC: G06F15/00 ,  G06F15/18 ,  G06N3/04

    CPC classification number: G11C16/26 ,  G06N3/04 ,  G06N3/0454 ,  G06N3/063 ,  G11C7/1006 ,  G11C7/106 ,  G11C16/0483 ,  G11C16/08

    Abstract: Devices, systems and methods for operating a memory device facilitating a neural network in a memory device are disclosed. In at least one embodiment, the memory device is operated having a feed-ward neural network operating scheme. In at least one other embodiment, memory cells are operated to emulate a number of neural models to facilitate one or more neural network operating characteristics in the memory device.

    Abstract translation: 公开了用于操作促进存储器件中的神经网络的存储器件的装置，系统和方法。 在至少一个实施例中，操作存储器装置具有馈送区神经网络操作方案。 在至少一个其他实施例中，存储器单元被操作以模拟许多神经模型以促进存储器件中的一个或多个神经网络操作特性。

    Single node power management for multiple memory devices
    43.
    发明授权
    Single node power management for multiple memory devices 有权
    用于多个存储器设备的单节点电源管理

    公开(公告)号：US09349423B2

    公开(公告)日：2016-05-24

    申请号：US14476323

    申请日：2014-09-03

    Applicant: Micron Technology, Inc.

    Inventor： Mauro Castelli ,  Luca De Santis ,  Luigi Pilolli ,  Maria Luisa Gallese

    IPC: G11C7/22 ,  G11C5/14

    CPC classification number: G11C7/222 ,  G11C5/04 ,  G11C5/14 ,  G11C7/062 ,  G11C8/10

    Abstract: Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on the memory cells, to cause at least one change in a level of a signal at the node in order to make a request to perform a particular stage of the operation such that the request is detectable by the memory devices, and to perform the particular stage of the operation after the request is acknowledged. Other embodiments are described.

    Abstract translation: 一些实施例包括具有耦合到多个存储器设备，存储器单元和模块以对存储器单元执行操作的节点的装置和方法，以使得在节点处的信号的电平的水平依次改变至少一个 以请求执行操作的特定阶段，使得该请求可由存储器件检测，并且在请求被确认之后执行操作的特定阶段。 描述其他实施例。

    Dynamic SLC/MLC blocks allocations for non-volatile memory
    44.
    发明授权
    Dynamic SLC/MLC blocks allocations for non-volatile memory 失效
    动态SLC / MLC阻止非易失性存储器的分配

    公开(公告)号：US08667215B2

    公开(公告)日：2014-03-04

    申请号：US13846638

    申请日：2013-03-18

    Applicant: Micron Technology, Inc.

    Inventor： Giulio Marotta ,  Luca De Santis ,  Tommaso Vali

    IPC: G06F12/00

    CPC classification number: G11C16/16 ,  G06F12/0246 ,  G06F2212/7202 ,  G11C2211/5641

    Abstract: Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode.

    Abstract translation: 公开了装置和方法，例如基于特性在单级单元（SLC）和多级单元（MLC）之间的NAND闪速存储器中提供动态块分配的装置和方法。 在一个实施例中，存储器控制器基于可用于使用的存储器的量，在SLC模式和MLC模式之间的编程和/或重新编程块之间动态切换。 当内存使用量低时，使用SLC模式。 当内存使用率高时，使用MLC模式。 动态块分配允许内存控制器获得SLC模式的性能和可靠性优势，同时保持MLC模式的节省空间的优势。

    Asynchronous interrupt event handling in multi-plane memory devices
    45.
    发明授权
    Asynchronous interrupt event handling in multi-plane memory devices 有权

    公开(公告)号：US11842078B2

    公开(公告)日：2023-12-12

    申请号：US17589080

    申请日：2022-01-31

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Giovanni Xotta ,  Guido Luciano Rizzo ,  Umberto Siciliani ,  Tommaso Vali ,  Luca De Santis ,  Walter Di Francesco

    IPC: G06F12/00 ,  G06F3/06 ,  G06F9/48

    CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F9/4812

    Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchronous interrupt event, and initiates a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times. In response to a first memory access operation of the plurality of asynchronous memory access operations ending, the control logic asserts a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes, and asserts a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.

    Checking status of multiple memory dies in a memory sub-system
    47.
    发明授权
    Checking status of multiple memory dies in a memory sub-system 有权

    公开(公告)号：US11681467B2

    公开(公告)日：2023-06-20

    申请号：US16946871

    申请日：2020-07-09

    Applicant: Micron Technology, Inc.

    Inventor： Luca Nubile ,  Luca De Santis

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

    Abstract: A processing device in a memory sub-system assigns each of a plurality of memory units associated with one or more memory die of a memory device a unique address by which each of the plurality of memory units is identified. The processing device further sends a multi-unit status command to the memory device, the multi-unit status command specifying a subset of the plurality of memory units using corresponding unique addresses and receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.

    ASYNCHRONOUS INTERRUPT EVENT HANDLING IN MULTI-PLANE MEMORY DEVICES
    48.
    发明申请
    ASYNCHRONOUS INTERRUPT EVENT HANDLING IN MULTI-PLANE MEMORY DEVICES 有权

    公开(公告)号：US20220405013A1

    公开(公告)日：2022-12-22

    申请号：US17589080

    申请日：2022-01-31

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Giovanni Xotta ,  Guido Luciano Rizzo ,  Umberto Siciliani ,  Tommaso Vali ,  Luca De Santis ,  Walter Di Francesco

    IPC: G06F3/06 ,  G06F9/48

    Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchronous interrupt event, and initiates a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times. In response to a first memory access operation of the plurality of asynchronous memory access operations ending, the control logic asserts a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes, and asserts a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.

    MEMORY DEVICES FOR PATTERN MATCHING
    49.
    发明申请
    MEMORY DEVICES FOR PATTERN MATCHING 有权

    公开(公告)号：US20210217475A1

    公开(公告)日：2021-07-15

    申请号：US17218243

    申请日：2021-03-31

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Vishal Sarin

    IPC: G11C15/04 ,  G11C16/10 ,  G11C16/04 ,  H01L27/00 ,  G11C13/06

    Abstract: Memory devices might include control circuitry that, when checking for a match of a stored digit of data and a received digit of data, might be configured to cause the memory device to apply a first voltage level to a control gate of a first memory cell of a memory cell pair, apply a second voltage level different than the first voltage level to a control gate of a second memory cell of that memory cell pair, determine whether that memory cell pair is deemed to be activated or deactivated in response to applying the first and second voltage levels, and deem a match between the stored digit of data and a received digit of data in response, in part, to whether that memory cell pair is deemed to be deactivated.

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