公开(公告)号：US20090227117A1

公开(公告)日：2009-09-10

申请号：US12421036

申请日：2009-04-09

申请人： Antonio L.P. Rotondaro ,  Luigi Colombo ,  Mark R. Visokay ,  Rajesh Khamankar ,  Douglas E. Mercer

发明人： Antonio L.P. Rotondaro ,  Luigi Colombo ,  Mark R. Visokay ,  Rajesh Khamankar ,  Douglas E. Mercer

IPC分类号： H01L21/31

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

摘要： A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.

摘要翻译： 一种MOSFET结构，包括在栅极材料沉积之前具有栅极电介质的氮化处理的硅酸盐栅极电介质。

公开(公告)号：US07183221B2

公开(公告)日：2007-02-27

申请号：US10703388

申请日：2003-11-06

申请人： Mark R. Visokay ,  Luigi Colombo

发明人： Mark R. Visokay ,  Luigi Colombo

IPC分类号： H01L21/302

CPC分类号： H01L21/823842

摘要： Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the metal layer. Atoms are incorporated into an exposed second portion of the metal layer to form a composition-altered portion of the metal layer. The mask layer is removed from the first portion of the metal layer and a barrier layer is deposited outwardly from the metal layer. A poly-Si layer is deposited outwardly from the barrier layer to form a semiconductor layer, where the barrier layer substantially prevents reaction of the metal layer with the poly-Si layer. The semiconductor layer is etched to form gate stacks, where each gate stack operates according to one of a plurality of work functions.

摘要翻译： 制造半导体包括从电介质层向外沉积金属层并从金属层的第一部分向外形成掩模层。 将原子并入金属层的暴露的第二部分中以形成金属层的组合物改变部分。 掩模层从金属层的第一部分去除，并且阻挡层从金属层向外沉积。 多晶硅层从阻挡层向外沉积形成半导体层，其中阻挡层基本上防止了金属层与多晶硅层的反应。 蚀刻半导体层以形成栅极堆叠，其中每个栅极堆叠根据多个功函数中的一个工作。

公开(公告)号：US06600183B1

公开(公告)日：2003-07-29

申请号：US09105830

申请日：1998-06-26

申请人： Mark R. Visokay ,  Luigi Colombo ,  Rajesh Khamankar ,  Mark A. Kressley

发明人： Mark R. Visokay ,  Luigi Colombo ,  Rajesh Khamankar ,  Mark A. Kressley

IPC分类号： H01L2976

CPC分类号： H01L21/7685 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7687 ,  H01L21/76889 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

摘要： An electrode structure for a capacitor. The electrode structure includes a contact plug comprising an oxidation barrier 208 and a bottom electrode comprising a conductive adhesion-promoting portion 210 and an oxidation-resistant portion 204, the adhesion-promoting portion contacting the oxidation barrier of the contact plug. In further embodiments, the oxidation barrier and adhesion-promoting portion comprise Ti—Al—N.

摘要翻译： 电容器的电极结构。 电极结构包括接触塞，其包括氧化屏障208和包括导电粘附促进部分210和抗氧化部分204的底部电极，所述粘合促进部分接触接触插塞的氧化屏障。 在另外的实施方案中，氧化屏障和增粘部分包括Ti-Al-N。

公开(公告)号：US07119386B2

公开(公告)日：2006-10-10

申请号：US11221103

申请日：2005-09-07

申请人： Mark R. Visokay ,  James J. Chambers

发明人： Mark R. Visokay ,  James J. Chambers

IPC分类号： H01L29/76

CPC分类号： H01L29/7831 ,  H01L29/66484

摘要： The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

摘要翻译： 本发明提供一种利用标准半导体衬底（302）制造三栅晶体管段（300）的系统。 衬底具有沿着其上表面以远侧分开的关系形成的多个隔离区域（304），其限定沟道区域（306）。 形式结构（308）设置在隔离区顶部，并且限定通道区域上的通道体区域（310）。 通道体结构（316）设置在通道主体区域内，并被设计成沿着其上暴露表面的周边提供钝角或边缘（318）。 然后去除形式结构，并执行后续处理。

公开(公告)号：US06969644B1

公开(公告)日：2005-11-29

申请号：US10930273

申请日：2004-08-31

申请人： Mark R. Visokay ,  James J. Chambers

发明人： Mark R. Visokay ,  James J. Chambers

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7831 ,  H01L29/66484

摘要： The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

摘要翻译： 本发明提供一种利用标准半导体衬底（302）制造三栅晶体管段（300）的系统。 衬底具有沿着其上表面以远侧分开的关系形成的多个隔离区域（304），其限定沟道区域（306）。 形式结构（308）设置在隔离区顶部，并且限定通道区域上的通道体区域（310）。 通道体结构（316）设置在通道主体区域内，并被设计成沿着其上暴露表面的周边提供钝角或边缘（318）。 然后去除形式结构，并执行后续处理。

公开(公告)号：US08389391B2

公开(公告)日：2013-03-05

申请号：US12696616

申请日：2010-01-29

申请人： James J. Chambers ,  Mark R. Visokay

发明人： James J. Chambers ,  Mark R. Visokay

IPC分类号： H01L21/3205

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： Example embodiments provide triple-gate semiconductor devices isolated by reverse shallow trench isolation (STI) structures and methods for their manufacture. In an example process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The example triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality.

摘要翻译： 示例性实施例提供通过反向浅沟槽隔离（STI）结构和其制造方法隔离的三栅极半导体器件。 在示例性工艺中，可以在半导体衬底上形成包括电介质层上的成形层的层叠层。 可以通过蚀刻穿过层叠层而形成一个或多个沟槽。 一个或多个沟槽可以由有源区域材料填充以形成一个或多个有源区域，其可以通过介电层的剩余部分来隔离。 通过去除表层可以暴露活性区域材料的物质。 然后可以在暴露的有源区域材料上形成一个或多个三栅极器件。 示例性三栅极半导体器件可以控制有源区域的尺寸并且在有源区域之间提供更小的隔离间隔，这优化了制造效率和器件集成质量。

公开(公告)号：US20090170258A1

公开(公告)日：2009-07-02

申请号：US11965024

申请日：2007-12-27

申请人： Aaron Frank ,  David Gonzalez, JR. ,  Mark R. Visokay ,  Clint Montgomery

发明人： Aaron Frank ,  David Gonzalez, JR. ,  Mark R. Visokay ,  Clint Montgomery

IPC分类号： H01L21/8238 ,  H01L21/28

CPC分类号： H01L21/823835 ,  H01L21/28097 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the p-type polysilicon has a first depth as measured from a top surface of the p-type polysilicon. An n-type dopant is implanted into the p-type polysilicon to form a counter-doped layer at the top-surface of the p-type polysilicon, where the counter-doped layer has a second depth that is less than the first depth. A catalyst metal is provided that associates with the counter-doped layer to form a catalytic surface. A metal is deposited over the catalytic surface. A thermal process is performed that reacts the metal with the p-type polysilicon in the presence of the catalytic surface to form a metal silicide. Other methods and devices are also disclosed.

摘要翻译： 一个实施例涉及一种制造集成电路的方法。 在该方法中，p型多晶硅设置在半导体本体上，其中p型多晶硅具有从p型多晶硅的顶表面测量的第一深度。 将n型掺杂剂注入到p型多晶硅中以在p型多晶硅的顶表面上形成反掺杂层，其中反掺杂层具有小于第一深度的第二深度。 提供催化剂金属，其与反掺杂层相结合以形成催化剂表面。 金属沉积在催化剂表面上。 进行热处理，其在催化剂表面存在下使金属与p型多晶硅反应形成金属硅化物。 还公开了其它方法和装置。

公开(公告)号：US20090032877A1

公开(公告)日：2009-02-05

申请号：US11832037

申请日：2007-08-01

申请人： Mark R. Visokay ,  Shaofeng Yu

发明人： Mark R. Visokay ,  Shaofeng Yu

IPC分类号： H01L21/8236 ,  H01L29/78

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L29/7847

摘要： A method of manufacturing a semiconductor device includes forming transistors including gate electrodes and source/drain regions over a substrate. A protective layer is placed over the source/drain regions and the gate electrodes. A portion of the protective layer is removed to expose a portion of the gate electrodes. The exposed portions of the gate electrodes are amorphized, and remaining portions of the protective layer located over the source/drain regions are removed. A stress memorization layer is formed over the gate electrodes, and the substrate is annealed in the presence of the stress memorization layer to at least reduce an amorphous content of the gate electrodes. The stress memorization layer is removed subsequent to the annealing.

摘要翻译： 制造半导体器件的方法包括在衬底上形成包括栅电极和源/漏区的晶体管。 保护层放置在源极/漏极区域和栅极电极之上。 去除保护层的一部分以露出栅电极的一部分。 栅电极的露出部分是非晶化的，并且去除位于源极/漏极区上方的保护层的剩余部分。 在栅电极上形成应力记忆层，并且在应力存储层的存在下对基板进行退火，以至少降低栅电极的无定形含量。 在退火之后去除应力记忆层。

公开(公告)号：US06617250B2

公开(公告)日：2003-09-09

申请号：US10243406

申请日：2002-09-13

申请人： Cem Basceri ,  Garo J. Derderian ,  Mark R. Visokay ,  John M. Drynan ,  Gurtej S. Sandhu

发明人： Cem Basceri ,  Garo J. Derderian ,  Mark R. Visokay ,  John M. Drynan ,  Gurtej S. Sandhu

IPC分类号： H01L21302

CPC分类号： H01L21/31122 ,  H01L21/28061 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/31604 ,  H01L21/32051 ,  H01L27/10811 ,  H01L27/10888 ,  H01L28/90 ,  H01L29/6659

摘要： In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta2O5 comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta2O5 comprising layer over a semiconductive substrate. The layer is exposed to WF6 under conditions effective to etch substantially amorphous Ta2O5 from the substrate. In one implementation, the layer is exposed to WF6 under conditions effective to both etch substantially amorphous Ta2O5 from the substrate and deposit a tungsten comprising layer over the substrate during the exposing.

摘要翻译： 部分地，公开了半导体处理方法，在衬底上沉积含钨层的方法，在衬底上沉积含氮化钨的层的方法，在衬底上沉积包含硅化钨的层的方法，形成晶体管栅极的方法 在衬底上划线，形成图案化的基本上结晶的Ta 2 O 5的材料的方法，以及形成包含基本上结晶的Ta 2 O 5的材料的电容器电介质区域的方法。 在一个实施方案中，半导体处理方法包括在半导体衬底上形成包含基本非晶态的Ta 2 O 5层。 该层在有效从底物上蚀刻基本无定形Ta 2 O 5的条件下暴露于WF6。 在一个实施方案中，该层在有效地从衬底上蚀刻基本上无定形Ta 2 O 5的条件下暴露于WF6，并在曝光期间在衬底上沉积含钨层。

公开(公告)号：US6159835A

公开(公告)日：2000-12-12

申请号：US543642

申请日：2000-04-06

申请人： Mark R. Visokay ,  Dirk N. Anderson

发明人： Mark R. Visokay ,  Dirk N. Anderson

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/66583 ,  H01L21/28061 ,  H01L29/4941

摘要： An encapsulated gate structure includes a polysilicon layer, a barrier layer overlying the polysilicon layer and having opposing sidewalls, a metal layer overlying the barrier layer and having opposing sidewalls, a top dielectric layer overlying the metal layer and having opposing sidewalls, and a vertically oriented dielectric layer extending over and covering each of the opposing sidewalls of the barrier layer and the metal layer to encapsulate the barrier layer and metal layer on the polysilicon layer. The encapsulated gate and barrier layer are thus unaffected by oxidation and other similar detrimental effects of subsequent processing steps.

摘要翻译： 封装的栅极结构包括多晶硅层，覆盖多晶硅层并具有相对侧壁的阻挡层，覆盖阻挡层并具有相对侧壁的金属层，覆盖金属层并具有相对侧壁的顶部电介质层和垂直定向 电介质层延伸并覆盖阻挡层和金属层的相对侧壁中的每一个，以将阻挡层和金属层封装在多晶硅层上。 因此，封装的栅极和阻挡层不受后续处理步骤的氧化和其它类似的有害影响的影响。