公开(公告)号：US08564120B2

公开(公告)日：2013-10-22

申请号：US12642989

申请日：2009-12-21

申请人： Anthony Mowry ,  David Farber ,  Fred Hause ,  Markus Lenski

发明人： Anthony Mowry ,  David Farber ,  Fred Hause ,  Markus Lenski

IPC分类号： H01L23/36 ,  H01L21/00

CPC分类号： H01L23/427 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/522 ,  H01L27/16 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00

摘要： By providing heat dissipation elements or heat pipes in temperature critical areas of a semiconductor device, enhanced performance, reliability and packing density may be achieved. The heat dissipation elements may be formed on the basis of standard manufacturing techniques and may be positioned in close proximity to individual transistor elements and/or may be used for shielding particular circuit portions.

摘要翻译： 通过在半导体器件的温度关键区域中提供散热元件或热管，可以实现增强的性能，可靠性和封装密度。 散热元件可以基于标准制造技术形成，并且可以定位成紧靠各个晶体管元件和/或可用于屏蔽特定的电路部分。

公开(公告)号：US20130234213A1

公开(公告)日：2013-09-12

申请号：US13415492

申请日：2012-03-08

申请人： Sivakumar KUMARASAMY ,  Clemens Fitz ,  Markus Lenski ,  Jochen Poth ,  Kristin Schupke

发明人： Sivakumar KUMARASAMY ,  Clemens Fitz ,  Markus Lenski ,  Jochen Poth ,  Kristin Schupke

IPC分类号： H01L21/66 ,  H01L29/68

CPC分类号： H01L21/28518 ,  H01L22/12 ,  H01L22/20

摘要： The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni'/Pt layer at a temperature of 130° C.

摘要翻译： 如果检测到Pt残留物，则通过执行包括在SWC工具中在130℃的温度下施加SPM的返工来减少形成含Pt的NiSi后剩余的Pt残余物的量。 实施例包括在半导体衬底上沉积一层Ni / Pt，退火沉积的Ni / Pt层，从退火的Ni / Pt层去除未反应的Ni，退火Ni去除的Ni / Pt层，从退火的Ni中除去未反应的Pt Ni / Pt层，分析未去除Pt残留物的Pt去除Ni / Pt层，如果检测到未反应的Pt残留物，则在SWC工具中将Pt施加到去除的Pt / Ni层上。 可以在130℃的温度下将SPM施加到Pt去除的Ni'/ Pt层上

公开(公告)号：US08507351B2

公开(公告)日：2013-08-13

申请号：US13152350

申请日：2011-06-03

申请人： Anthony Mowry ,  Markus Lenski ,  Guido Koerner ,  Ralf Otterbach

发明人： Anthony Mowry ,  Markus Lenski ,  Guido Koerner ,  Ralf Otterbach

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.

摘要翻译： 通过例如通过基于注入掩模减小间隔物宽度来选择性地修改间隔物宽度，可以实现单独的掺杂剂轮廓的适应性，而不会不利地导致整个工艺复杂性。 例如，在复杂的集成电路中，相同或不同导电类型的晶体管的性能可以通过基于适当的掩蔽状态提供不同的侧壁间隔物宽度来单独调节。

公开(公告)号：US08298894B2

公开(公告)日：2012-10-30

申请号：US12785185

申请日：2010-05-21

申请人： Markus Lenski ,  Klaus Hempel ,  Vivien Schroeder ,  Robert Binder ,  Joachim Metzger

发明人： Markus Lenski ,  Klaus Hempel ,  Vivien Schroeder ,  Robert Binder ,  Joachim Metzger

IPC分类号： H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/82345 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： In a replacement gate approach in sophisticated semiconductor devices, a tantalum nitride etch stop material may be efficiently removed on the basis of a wet chemical etch recipe using ammonium hydroxide. Consequently, a further work function adjusting material may be formed with superior uniformity, while the efficiency of the subsequent adjusting of the work function may also be increased. Thus, superior uniformity, i.e., less pronounced transistor variability, may be accomplished on the basis of a replacement gate approach in which the work function of the gate electrodes of P-channel transistors and N-channel transistors is adjusted after completing the basic transistor configuration.

摘要翻译： 在复杂半导体器件中的替代栅极方法中，可以基于使用氢氧化铵的湿化学蚀刻配方有效地去除氮化钽蚀刻停止材料。 因此，可以形成具有优异均匀性的另外的功能调节材料，同时可以提高随后的功函数调整的效率。 因此，可以在替代栅极方法的基础上实现优异的均匀性，即较不明显的晶体管可变性，其中在完成基本晶体管配置之后调节P沟道晶体管和N沟道晶体管的栅电极的功函数 。

公开(公告)号：US08183605B2

公开(公告)日：2012-05-22

申请号：US12791290

申请日：2010-06-01

申请人： Thomas Feudel ,  Markus Lenski ,  Andreas Gehring

发明人： Thomas Feudel ,  Markus Lenski ,  Andreas Gehring

IPC分类号： H01L29/80 ,  H01L27/01 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/425

CPC分类号： H01L21/324 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78621

摘要： By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

摘要翻译： 通过基于间隔结构凹陷漏极和源极区域的部分，用于形成深漏极和源极区域的后续注入工艺可导致向下延伸到SOI晶体管的掩埋绝缘层的适度高的掺杂剂浓度。 此外，间隔结构保持大量的具有其原始厚度的应变半导体合金，从而提供有效的应变诱导机制。 通过使用复杂的退火技术，可以避免不适当的横向扩散，从而允许减小各个间隔物的横向宽度，从而减小晶体管器件的长度。 因此，可以基于减小的横向尺寸来实现增强的载流子迁移率与减少的结电容的组合。

公开(公告)号：US20110186931A1

公开(公告)日：2011-08-04

申请号：US12914234

申请日：2010-10-28

申请人： Gerd Marxsen ,  Joachim Metzger ,  Robert Binder ,  Markus Lenski

发明人： Gerd Marxsen ,  Joachim Metzger ,  Robert Binder ,  Markus Lenski

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

摘要： In a replacement gate approach, one work function metal may be provided in an early manufacturing stage, i.e., upon depositing the gate layer stack, thereby reducing the number of deposition steps required in a later manufacturing stage. Consequently, the further work function metal and the electrode metal may be filled into the gate trenches on the basis of superior process conditions compared to conventional replacement gate approaches.

摘要翻译： 在替代栅极方法中，可以在早期制造阶段（即，在沉积栅极层堆叠时）提供一个功函数金属，从而减少后续制造阶段所需的沉积步骤的数量。 因此，与传统的替代栅极方法相比，基于优越的工艺条件，可以将另外的功函数金属和电极金属填充到栅极沟槽中。

公开(公告)号：US07977179B2

公开(公告)日：2011-07-12

申请号：US12108992

申请日：2008-04-24

申请人： Anthony Mowry ,  Markus Lenski ,  Guido Koerner ,  Ralf Otterbach

发明人： Anthony Mowry ,  Markus Lenski ,  Guido Koerner ,  Ralf Otterbach

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.

摘要翻译： 通过例如通过基于注入掩模减小间隔物宽度来选择性地修改间隔物宽度，可以实现单独的掺杂剂轮廓的适应性，而不会不利地导致整个工艺复杂性。 例如，在复杂的集成电路中，相同或不同导电类型的晶体管的性能可以通过基于适当的掩蔽状态提供不同的侧壁间隔物宽度来单独调节。

公开(公告)号：US20110024914A1

公开(公告)日：2011-02-03

申请号：US12844263

申请日：2010-07-27

申请人： Stephan Kronholz ,  Markus Lenski ,  Ralf Richter

发明人： Stephan Kronholz ,  Markus Lenski ,  Ralf Richter

IPC分类号： H01L23/48 ,  H01L21/50 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/8221 ,  H01L23/53276 ,  H01L27/0688 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/80001

摘要： In a stacked chip configuration, the “inter chip” connection is established on the basis of functional molecules, thereby providing a fast and space-efficient communication between the different semiconductor chips.

摘要翻译： 在堆叠式芯片配置中，基于功能分子建立“芯片间”连接，从而在不同半导体芯片之间提供快速且空间有效的通信。

公开(公告)号：US20100301421A1

公开(公告)日：2010-12-02

申请号：US12772436

申请日：2010-05-03

申请人： Stephan Kronholz ,  Markus Lenski ,  Vassilios Papageorgiou

发明人： Stephan Kronholz ,  Markus Lenski ,  Vassilios Papageorgiou

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51

摘要： Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region.

摘要翻译： 基于嵌入式应变诱发半导体合金，可以通过基于高k介电材料与含金属盖层组合形成栅电极结构来增强P沟道晶体管的性能，以获得 栅电极结构的底切配置。 因此，应变诱导半导体合金可以基于最小厚度的侧壁间隔物形成，以便使应变诱导半导体材料更靠近沟道区的中心区域。

公开(公告)号：US07754556B2

公开(公告)日：2010-07-13

申请号：US12027583

申请日：2008-02-07

申请人： Thomas Feudel ,  Markus Lenski ,  Andreas Gehring

发明人： Thomas Feudel ,  Markus Lenski ,  Andreas Gehring

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/425 ,  H01L29/80 ,  H01L27/10

CPC分类号： H01L21/324 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78621

摘要： By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

摘要翻译： 通过基于间隔结构凹陷漏极和源极区域的部分，用于形成深漏极和源极区域的后续注入工艺可导致向下延伸到SOI晶体管的掩埋绝缘层的适度高的掺杂剂浓度。 此外，间隔结构保持大量的具有其原始厚度的应变半导体合金，从而提供有效的应变诱导机制。 通过使用复杂的退火技术，可以避免不适当的横向扩散，从而允许减小各个间隔物的横向宽度，从而减小晶体管器件的长度。 因此，可以基于减小的横向尺寸来实现增强的载流子迁移率与减少的结电容的组合。