公开(公告)号：US20050077559A1

公开(公告)日：2005-04-14

申请号：US10752503

申请日：2004-01-08

申请人： Masaru Kito ,  Hideaki Aochi

发明人： Masaru Kito ,  Hideaki Aochi

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L29/94 ,  H01L29/76 ,  H01L21/20

CPC分类号： H01L27/10867 ,  H01L29/945

摘要： A trench capacitor comprises a semiconductor substrate, a trench, formed in the semiconductor substrate, having upper and lower portions, a first doped polysilicon layer filled in the lower portion through a first dielectric film and doped with a first impurity having a first conductivity type, at least a second doped polysilicon layer filled in the upper portion through a second dielectric film and doped with a second impurity different from the first impurity, the second impurity having the first conductivity type, and a buried strap layer provided on the second doped polysilicon layer and composed of the first doped polysilicon layer.

摘要翻译： 沟槽电容器包括形成在半导体衬底中的半导体衬底，沟槽，具有上部和下部，通过第一电介质膜填充在下部的第一掺杂多晶硅层，并掺杂有具有第一导电类型的第一杂质， 至少第二掺杂多晶硅层，其通过第二电介质膜填充在上部，并且掺杂有不同于第一杂质的第二杂质，第二杂质具有第一导电类型，以及设置在第二掺杂多晶硅层上的掩埋带层 并由第一掺杂多晶硅层组成。

公开(公告)号：US5414234A

公开(公告)日：1995-05-09

申请号：US148053

申请日：1993-11-05

申请人： Masaru Kito

发明人： Masaru Kito

IPC分类号： B23K9/20

CPC分类号： B23K9/201

摘要： A welding comprises placing the end of a stud supported by a welding gun on a welding portion of a workpiece, producing an arc discharge across the stud and the workpiece, melting the end of the stud and a portion of the workpiece and bringing the end of the stud so as to abut on the melted portion of the workpiece. A hollow cylindrical member 21 is prepared so that the material has a larger inside diameter than an end 20 of a stud 19 and is made of a magnetic permeable material is prepared. During the arc discharge, the cylindrical member 21 is placed so that the hollow portion is positioned on the side of the workpiece opposite to the stud and corresponding to the end of the stud.

摘要翻译： 焊接包括将由焊枪支撑的螺柱的端部放置在工件的焊接部分上，从而产生穿过螺柱和工件的电弧放电，熔化螺柱的端部和工件的一部分，并使 螺柱，以便抵靠在工件的熔化部分上。 制备中空的圆柱形构件21，使得该材料具有比螺柱19的端部20更大的内径，并且由导磁材料制成。 在电弧放电期间，圆柱形部件21被放置成使得中空部分位于工件的与螺柱相对的侧面并且对应于螺柱的端部。

公开(公告)号：US09025377B2

公开(公告)日：2015-05-05

申请号：US13052195

申请日：2011-03-21

申请人： Kunihiro Yamada ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Yoshiaki Fukuzumi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Kaori Kawasaki

发明人： Kunihiro Yamada ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Yoshiaki Fukuzumi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Kaori Kawasaki

IPC分类号： G11C16/22 ,  G11C16/04 ,  H01L27/115

CPC分类号： G11C16/0483 ,  G11C16/22 ,  H01L27/11578 ,  H01L27/11582

摘要： According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.

摘要翻译： 根据一个实施例，公开了一种操作半导体存储器件的方法。 该方法可以包括将至少一个从通过主体连接的多个存储单元的最上层的存储单元和最下层的存储单元中选出的至少一个存储在只读数据中。 通道体从衬底向上延伸以与堆叠在衬底上的多个电极层交叉。 该方法可以包括禁止具有存储在只读存储器单元中的只读数据的只读存储器单元的数据擦除操作。

公开(公告)号：US08786008B2

公开(公告)日：2014-07-22

申请号：US13420745

申请日：2012-03-15

申请人： Megumi Ishiduki ,  Masaru Kidoh ,  Mitsuru Sato ,  Masaru Kito ,  Ryota Katsumata

发明人： Megumi Ishiduki ,  Masaru Kidoh ,  Mitsuru Sato ,  Masaru Kito ,  Ryota Katsumata

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/7926 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/42344

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body; a memory film; a first channel body layer provided inside the memory film; an interlayer insulating film provided on the first stacked body; a second stacked body having a select gate electrode layer, and a second insulating layer; a gate insulating film provided on a side wall of a second hole communicating with the first hole and penetrating the second stacked body and the interlayer insulating film in a stacking direction of the second stacked body; and a second channel body layer provided inside the gate insulating film in the second hole. A first pore diameter of the second hole at an upper end of the select gate electrode layer is smaller than a second pore diameter of the second hole at an lower end of the select gate electrode layer.

摘要翻译： 根据一个实施例，一种非易失性半导体存储器件包括：第一层叠体; 记忆膜; 设置在记忆膜内部的第一通道体层; 设置在所述第一层叠体上的层间绝缘膜; 具有选择栅电极层的第二层叠体和第二绝缘层; 栅极绝缘膜，设置在与所述第一孔连通的第二孔的侧壁上，并且在所述第二层叠体的层叠方向上贯通所述第二层叠体和所述层间绝缘膜; 以及设置在第二孔中的栅极绝缘膜内部的第二沟道体层。 选择栅电极层的上端的第二孔的第一孔径比选择栅电极层的下端的第二孔的第二孔径小。

公开(公告)号：US08767452B2

公开(公告)日：2014-07-01

申请号：US13418651

申请日：2012-03-13

申请人： Masaru Kito ,  Tomoko Fujiwara ,  Hideaki Aochi

发明人： Masaru Kito ,  Tomoko Fujiwara ,  Hideaki Aochi

IPC分类号： G11C11/14 ,  G11C11/00

CPC分类号： H01L27/11565 ,  G11C5/025 ,  H01L27/11582 ,  H01L29/7926

摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a charge storage layer, a tunneling layer, a dividing trench and a first heating unit. The stacked body includes a plurality of first insulating films stacked alternately with a plurality of electrode films. The semiconductor pillar pierces the stacked body. The charge storage layer is provided between the electrode films and the semiconductor pillar. The tunneling layer is provided between the charge storage layer and the semiconductor pillar. The dividing trench is provided between the semiconductor pillars in one direction orthogonal to a stacking direction of the stacked body to divide the electrode films. The first heating unit is provided in an interior of the dividing trench.

摘要翻译： 根据一个实施例，半导体存储器件包括堆叠体，半导体柱，电荷存储层，隧道层，分隔沟槽和第一加热单元。 层叠体包括与多个电极膜交替堆叠的多个第一绝缘膜。 半导体柱穿透层叠体。 电荷存储层设置在电极膜和半导体柱之间。 隧道层设置在电荷存储层和半导体柱之间。 在与层叠体的堆叠方向正交的一个方向上的半导体柱之间设置分割沟槽，以分割电极膜。 第一加热单元设置在分隔沟槽的内部。

公开(公告)号：US08766351B2

公开(公告)日：2014-07-01

申请号：US13112345

申请日：2011-05-20

申请人： Takeshi Imamura ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Ryouhei Kirisawa

发明人： Takeshi Imamura ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Ryouhei Kirisawa

IPC分类号： H01L29/788

CPC分类号： H01L27/11556 ,  H01L29/42324 ,  H01L29/7889

摘要： According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.

摘要翻译： 根据一个实施例，提供了柱状半导体，通过隧道电介质膜形成在柱状半导体的侧表面上的浮栅电极和通过块状电介质膜包围浮置栅电极的控制栅电极。

公开(公告)号：US08728919B2

公开(公告)日：2014-05-20

申请号：US13723601

申请日：2012-12-21

申请人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Megumi Ishiduki ,  Yosuke Komori ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi

发明人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Megumi Ishiduki ,  Yosuke Komori ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi

IPC分类号： H01L21/20

CPC分类号： H01L29/7926 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7881

摘要： A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.

摘要翻译： 非挥发性半导体存储装置包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元。 每个存储器串包括：第一半导体层，包括相对于衬底在垂直方向上延伸的柱状部分; 多个第一导电层，经由绝缘层形成为围绕柱状部分的侧表面，并以垂直方向上的一定间距形成，第一导电层用作存储器单元的浮动栅极; 以及形成为经由绝缘层包围第一导电层并且用作存储单元的控制电极的多个第二导电层。 每个第一导电层在垂直方向上具有比每个第二导电层的垂直方向上的长度短的长度。

公开(公告)号：US08674430B2

公开(公告)日：2014-03-18

申请号：US13428111

申请日：2012-03-23

申请人： Naoki Yasuda ,  Masaru Kito

发明人： Naoki Yasuda ,  Masaru Kito

IPC分类号： H01L29/792

CPC分类号： H01L27/1157 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792 ,  H01L29/7926

摘要： According to one embodiment, a control gate is formed on the semiconductor substrate and includes a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. The tunnel insulating film comprises a first insulating film having SiO2 as a base material and containing an element that lowers a band gap of the base material by being added. A density and a density gradient of the element monotonously increase from the semiconductor layer toward the charge storage film.

摘要翻译： 根据一个实施例，控制栅极形成在半导体衬底上并且包括圆柱形通孔。 在通孔内的控制栅极的侧表面上形成块绝缘膜，电荷存储膜，隧道绝缘膜和半导体层。 隧道绝缘膜包括具有SiO 2作为基材的第一绝缘膜，并且包含通过添加来降低基材的带隙的元素。 元素的密度和密度梯度从半导体层向电荷存储膜单调增加。

公开(公告)号：US08514627B2

公开(公告)日：2013-08-20

申请号：US13235389

申请日：2011-09-18

申请人： Kiyotaro Itagaki ,  Masaru Kito ,  Ryu Ogiwara ,  Hitoshi Iwai

发明人： Kiyotaro Itagaki ,  Masaru Kito ,  Ryu Ogiwara ,  Hitoshi Iwai

IPC分类号： G11C16/04

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/344 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

摘要： A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.

摘要翻译： 控制电路被配置为对选择的存储块中的所选择的单元单元执行擦除操作。 在擦除操作中，控制电路将包括在所选择的单元单元中的第一存储晶体管的主体的电压升高到第一电压，将未选择的单元单元中包括的第一存储晶体管的主体的电压设置为 第二电压低于第一电压，并将等于或低于第二电压的第三电压施加到所选择的单元单元和未选择的单元单元中包括的第一存储晶体管的栅极。

公开(公告)号：US08436414B2

公开(公告)日：2013-05-07

申请号：US12706127

申请日：2010-02-16

申请人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Junya Matsunami ,  Ryouhei Kirisawa

发明人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Junya Matsunami ,  Ryouhei Kirisawa

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 设置在所述半导体基板上的层叠体，具有交替堆叠的电极膜和绝缘膜的层叠体， 第一和第二半导体柱; 以及第一和第二电荷存储层。 第一半导体柱和第二半导体柱设置在层叠体的层叠方向上贯穿层叠体的贯通孔内。 当沿垂直于堆叠方向的方向切割时，通孔具有扁圆形的横截面。 第一和第二半导体柱在第一扁圆的长轴方向上彼此面对。 第一和第二半导体柱沿层叠方向延伸。 第一和第二电荷存储层分别设置在电极膜和第一和第二半导体柱之间。