公开(公告)号：US5325506A

公开(公告)日：1994-06-28

申请号：US948513

申请日：1992-09-22

申请人： Mamoru Tohchi ,  Akira Kurano ,  Hisaharu Takeuchi ,  Yukihisa Kashima ,  Ikuo Kawaguchi

发明人： Mamoru Tohchi ,  Akira Kurano ,  Hisaharu Takeuchi ,  Yukihisa Kashima ,  Ikuo Kawaguchi

IPC分类号： G06F3/06 ,  G11B19/02 ,  G11B19/20 ,  G11B20/10 ,  G11B27/10 ,  G11B15/12

CPC分类号： G11B19/20 ,  G06F3/0601 ,  G11B19/02 ,  G11B27/105 ,  G06F2003/0692

摘要： An external memory device subsystem and a data recording device, which issue a command specifying previously a plurality of tracks in a rotary type memory device prior to a read or write instruction issued from the data processing unit of higher rank to the rotary type memory device through a control unit; select continuously the plurality of tracks previously specified, at executing a read or write command after the execution of the command; and in this way can read/write continuously without wait time for rotation a plurality of tracks distant from each other within the same cylinder.

摘要翻译： 一种外部存储器件子系统和数据记录装置，其在从旋转式存储装置的较高等级的数据处理单元发出的读取或写入指令之前发出在旋转型存储装置中预先指定多个轨迹的命令， 一个控制单元; 在执行命令后执行读或写命令，连续选择先前指定的多个轨道; 并且以这种方式可以连续读/写，而无需等待时间旋转在同一气缸内彼此远离的多个轨道。

公开(公告)号：US4951137A

公开(公告)日：1990-08-21

申请号：US331319

申请日：1989-03-31

申请人： Masaaki Kisou ,  Kenji Shimoda ,  Kazumasa Ikeda ,  Shinji Yoda ,  Hisaharu Takeuchi

发明人： Masaaki Kisou ,  Kenji Shimoda ,  Kazumasa Ikeda ,  Shinji Yoda ,  Hisaharu Takeuchi

IPC分类号： H04N5/21

CPC分类号： H04N5/21

摘要： Image track display apparatus including a memory for delaying an image signal by at least one vertical scanning period, a first subtraction circuit for taking a first difference signal between the image signal and its delayed image signal through the memory. The first difference signal includes first and second polarity components, a non-linear processing circuit for multiplying the one polarity component of the first difference signal by K times (0

摘要翻译： 图像轨迹显示装置，包括用于将图像信号延迟至少一个垂直扫描周期的存储器，第一减法电路，用于通过存储器获取图像信号和其延迟图像信号之间的第一差分信号。 第一差分信号包括第一和第二极性分量，用于将第一差分信号的一个极性分量乘以K倍（0

公开(公告)号：US20100332782A1

公开(公告)日：2010-12-30

申请号：US12923156

申请日：2010-09-07

申请人： Shintaro Inoue ,  Yutaka Takata ,  Mikio Fukuoka ,  Eiju Katsuragi ,  Hisaharu Takeuchi

发明人： Shintaro Inoue ,  Yutaka Takata ,  Mikio Fukuoka ,  Eiju Katsuragi ,  Hisaharu Takeuchi

IPC分类号： G06F12/16 ,  G06F12/00

CPC分类号： G06F3/0665 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/067 ,  G06F3/0683

摘要： A virtualization system, upon judging that a write operation from a higher-level device is an operation to write in the format of the virtual volume, even when the write position of the write operation is in a virtual area different from a virtual area to which an allocated actual area has been allocated, if there is an unused area in the allocated actual area, writes management information to the unused area according to the write operation, and if there is no unused area in the allocated actual area, newly allocates an unallocated actual area, and writes management information to the newly allocated actual area according to the write operation.

摘要翻译： 虚拟化系统在判断来自较高级设备的写入操作是以虚拟卷的格式写入的操作时，即使当写入操作的写入位置在与虚拟区域不同的虚拟区域中时， 如果分配的实际区域中存在未使用区域，则根据写入操作将管理信息写入未使用区域，并且如果在所分配的实际区域中没有未使用区域，则新分配未分配的实际区域 实际区域，并根据写入操作将管理信息写入新分配的实际区域。

公开(公告)号：US07849258B2

公开(公告)日：2010-12-07

申请号：US11970839

申请日：2008-01-08

申请人： Kei Sato ,  Hisaharu Takeuchi

发明人： Kei Sato ,  Hisaharu Takeuchi

IPC分类号： G06F12/00

CPC分类号： G06F11/0727 ,  G06F11/0763

摘要： A controller unit for the storage apparatus executes the following: giving each data block, which is a data constituent unit, an identification number indicating that the relevant data has been sent from a host computer in response to an arbitrary write request from the host computer; storing, in a memory unit, a storage location in a hard disk drive unit to store the data, as well as the identification number, as an expected value, for the data to be stored in the hard disk drive unit; and in response to a read request from the host computer, comparing the identification number given to each data block, the constituent unit of the data read from the hard disk drive unit, with the expected value of the read data, thereby verifying that the read data is the data written to the hard disk drive in response to the arbitrary write request.

摘要翻译： 用于存储装置的控制器单元执行以下操作：响应于来自主计算机的任意写入请求，给作为数据构成单元的每个数据块指示相应数据已经从主计算机发送的标识号; 将存储在硬盘驱动器单元中的存储位置存储在存储器单元中以将数据存储在存储在硬盘驱动器单元中的数据以及作为期望值的识别号码; 并且响应于来自主计算机的读取请求，将从硬盘驱动器单元读取的数据的构成单元与给定的每个数据块的识别号码与读取的数据的预期值进行比较，从而验证读取 数据是响应于任意写请求而写入硬盘驱动器的数据。

公开(公告)号：US20090198942A1

公开(公告)日：2009-08-06

申请号：US12060977

申请日：2008-04-02

申请人： Noboru Morishita ,  Akira Deguchi ,  Ai Satoyama ,  Hisaharu Takeuchi

发明人： Noboru Morishita ,  Akira Deguchi ,  Ai Satoyama ,  Hisaharu Takeuchi

IPC分类号： G06F12/06

CPC分类号： G06F3/0665 ,  G06F3/0605 ,  G06F3/067 ,  G06F11/0727 ,  G06F11/0793 ,  G06F11/2007 ,  G06F11/201

摘要： A plurality of global LDEV managed by a plurality of controller modules are provided above local LDEV under the control of each controller module. Each global LDEV is correlated to any of the plurality of local LDEV. The controller modules judge whether or not a local LDEV correlated to a global LDEV specified by an I/O request received from a host device or a first other controller module is a management target itself, and if the result of that judgment is affirmative, the controller modules access the local LDEV correlated to the specified global LDEV, while if the result of the judgment is negative, the controller modules transfer the received I/O request to a second other controller module.

摘要翻译： 由多个控制器模块管理的多个全局LDEV被设置在每个控制器模块的控制下的局部LDEV之上。 每个全局LDEV与多个本地LDEV中的任一个相关联。 控制器模块判断与从主机设备或第一其他控制器模块接收到的I / O请求指定的全局LDEV相关的本地LDEV是否是管理目标本身，如果判断结果是肯定的，则 控制器模块访问与指定的全局LDEV相关的本地LDEV，而如果判断结果为否定，则控制器模块将接收的I / O请求传输到另一个其他控制器模块。

公开(公告)号：US20050273647A1

公开(公告)日：2005-12-08

申请号：US10877345

申请日：2004-06-25

申请人： Noboru Furuumi ,  Hisaharu Takeuchi

发明人： Noboru Furuumi ,  Hisaharu Takeuchi

IPC分类号： G06F13/10 ,  G06F3/06 ,  G06F11/00 ,  G06F12/00 ,  G06F13/14

CPC分类号： G06F3/062 ,  G06F3/0617 ,  G06F3/0635 ,  G06F3/067

摘要： A personal computer inputs path information for forming a path group and a storage controller manages the path group. For example, a physical path PS#1, a path PS#2 and a path PS#3 are defined as a path group PG#1 and instructed to the storage controller. This indication is stored in a table. Host A recognizes this path group information, too. Host A designates “Persistent Reserve OUT” on the path PS#1. The storage controller recognizes that the path group PG#1 inclusive of this path PS#1 is reserved as a whole. When Host B attempts release this reserve state illegally through a path PS#1 of Host A, Host B issues “Persistent Reserve OUT” command by KEY#1. Because the path PS#1 does not belong to the path group managed by the storage controller, however, the reserve release request is rejected.

摘要翻译： 个人计算机输入用于形成路径组的路径信息，存储控制器管理路径组。 例如，物理路径PS＃1，路径PS＃2和路径PS＃3被定义为路径组PG＃1，并被指示给存储控制器。 该指示存储在表中。 主机A也识别此路径组信息。 主机A在路径PS＃1上指定“持久保留OUT”。 存储控制器识别出包含该路径PS＃1的路径组PG＃1整体被保留。 当主机B尝试通过主机A的路径PS＃1非法释放该保留状态时，主机B发出KEY＃1的“持久保留OUT”命令。 由于路径PS＃1不属于由存储控制器管理的路径组，所以保留释放请求被拒绝。

公开(公告)号：US20050076162A1

公开(公告)日：2005-04-07

申请号：US10803204

申请日：2004-03-17

申请人： Misako Tamura ,  Hisaharu Takeuchi ,  Noboru Furuumi

发明人： Misako Tamura ,  Hisaharu Takeuchi ,  Noboru Furuumi

IPC分类号： G06F3/06 ,  G06F3/00 ,  G06F13/38

CPC分类号： G06F13/387

摘要： The value relating to the average of the length of processing time required to process a plurality of information sets is reduced. The information processing device comprises: a receiving component receiving information elements contained in respective information sets having one or more information elements, from one or a plurality of information set sources issuing the information sets; an information processing component carrying out processing of the information elements thus received; and a determining component determining a processing sequence for the two or more information sets or the plurality of information elements, on the basis of the plurality of information elements that are unprocessed or currently being processed, contained in two or more information sets thus received, and determining a processing sequence different from the reception sequence, in which a value relating to the average of the length of processing time for the two or more information sets becomes equal to or less than the value that would be obtained were the plurality of information elements or the two or more information sets to be processed in accordance with their reception sequence; the processing of a plurality of information elements that are unprocessed or currently being processed, being started on the basis of the processing sequence thus determined.

摘要翻译： 与处理多个信息集所需的处理时间的长度的平均值相关的值减小。 所述信息处理装置包括：从发出所述信息集的一个或多个信息集源中接收包含在具有一个或多个信息元素的各个信息集中的信息元素的接收部件; 信息处理部件，对由此接收到的信息元素进行处理; 以及确定部件，其基于由所接收的两个或更多个信息集合中的未被处理或当前被处理的多个信息元素确定用于所述两个或多个信息集或所述多个信息元素的处理序列，以及 确定与所述接收序列不同的处理序列，其中与所述两个或更多个信息集合的处理时间的长度的平均值相关的值变为等于或小于将获得的值为多个信息元素或 要根据其接收顺序处理的两个或多个信息集; 基于如此确定的处理顺序开始处理未处理或正在处理的多个信息元素。

公开(公告)号：US06607995B1

公开(公告)日：2003-08-19

申请号：US09581635

申请日：2000-06-15

申请人： Hisaharu Takeuchi ,  Tsuneo Igarashi ,  Hiroyuki Mizuki

发明人： Hisaharu Takeuchi ,  Tsuneo Igarashi ,  Hiroyuki Mizuki

IPC分类号： D03D1500

CPC分类号： D03D15/00 ,  A41D27/02 ,  D03D15/0027 ,  D03D15/0061 ,  D03D15/0077 ,  D03D15/0083 ,  D03D15/12 ,  D10B2331/04 ,  D10B2401/14 ,  D10B2401/16 ,  D10B2501/06 ,  Y10T442/3179 ,  Y10T442/322 ,  Y10T442/326 ,  Y10T442/3268 ,  Y10T442/3285 ,  Y10T442/3976

摘要： A lining cloth of a woven fabric in which the warp yarn comprises either of polyester filamentary yarn or cellulosic filamentary yarn and the filling yarn comprises either a false-twisted polyester filamentary yarn, a raw filamentary yarn or a cellulosic filamentary yarn, characterized in that an elongation in the filling-wise direction of the woven fabric is in a range from 5% to 12%, a coefficient of dynamic friction on the surface of the woven fabric is in a range from 0.20 to 0.45, and a filling-wise crimp index value of the woven fabric as defined by the following formula (1) is in a range from 0.003 to 0.013: Crimp ratio of the filling yarn/{warp density×(warp fineness)1/2}  (1) The lining cloth according to the present invention is soft in touch, excellent in slipperiness, resistant to seam slippage and free from wearing pressure. The lining cloth is suitably used as a lining for a skirt which is otherwise liable to ride up. The lining cloth according to the present invention is produced by heat-treating a grey fabric woven from warp yarns of polyester filament or cellulosic filament and filling yarns of raw polyester filament at a temperature in a range from 160° C. to 210° C. prior to or after the scouring while being narrowed in width by 5 to 30% relative to the grey fabric.

摘要翻译： 一种编织物的衬里布，其中经纱包括聚酯长丝纱线或纤维素丝线纱中的任一种，并且填充纱线包括假捻聚酯长丝纱线，原丝线纱或纤维素丝线纱，其特征在于， 机织织物的填充方向的伸长率在5％〜12％的范围内，织物表面的动摩擦系数在0.20〜0.45的范围内，填充卷曲指数 由下式（1）定义的织物的值在0.003〜0.013的范围内。本发明的衬布柔软，滑动性优异，耐缝合滑动，不受磨损压力的影响。 衬里布适合用作裙子的衬里，否则其可能容易骑行。根据本发明的衬里布通过热处理由聚酯长丝或纤维素长丝的经纱编织的坯布和填充纱线 的原料聚酯长丝，在精练之前或之后的温度范围为160℃至210℃，同时相对于灰色织物的宽度变窄5至30％。

公开(公告)号：US5689728A

公开(公告)日：1997-11-18

申请号：US395766

申请日：1989-08-18

申请人： Shuji Sugimoto ,  Norio Hamada ,  Yoshiro Shiroyanagi ,  Hisaharu Takeuchi

发明人： Shuji Sugimoto ,  Norio Hamada ,  Yoshiro Shiroyanagi ,  Hisaharu Takeuchi

IPC分类号： G06F3/06 ,  G06F12/08 ,  G06F13/10 ,  G06F13/38

CPC分类号： G06F12/0866 ,  G06F13/385

摘要： In a magnetic disk controller equipped with a cache memory for disks, the controller in accordance with the present invention includes high order paths for data transfer between a high order channel apparatus and the cache memory through a certain one of a plurality of channel adaptors, low order paths for data transfer between a low order device, e.g. a magnetic disk device, and the cache memory through a certain one of a plurality of device adaptors and a path for data transfer betweeen the low order device and the channel cevice without passing through the cache memory by selecting empty device adaptor and channel adaptor by the switching operation of a switch. When an interrupt is generated from the device, data transfer can be made easily even when the high order path and the low order path are busy, and path utilization efficiency can be improved.

摘要翻译： 在配备有用于盘的高速缓冲存储器的磁盘控制器中，根据本发明的控制器包括用于通过多个通道适配器中的某一个的高阶通道设备和高速缓冲存储器之间的数据传输的高阶路径，低 低阶设备之间的数据传输的订单路径，例如 磁盘装置和高速缓冲存储器，通过多个设备适配器中的某一个和用于在低阶设备和信道接入之间的数据传输的路径而不通过高速缓存存储器，通过选择空的设备适配器和通道适配器 开关的切换操作。 当从设备产生中断时，即使当高阶路径和低阶路径繁忙时也可以容易地进行数据传送，并且可以提高路径利用效率。

公开(公告)号：US5640600A

公开(公告)日：1997-06-17

申请号：US381560

申请日：1995-01-31

申请人： Takao Satoh ,  Hisaharu Takeuchi ,  Yasuo Inoue ,  Akira Yamamoto

发明人： Takao Satoh ,  Hisaharu Takeuchi ,  Yasuo Inoue ,  Akira Yamamoto

IPC分类号： G06F13/16 ,  G06F3/06 ,  G06F11/34 ,  G06F13/12 ,  G06F13/36 ,  H01J3/00

CPC分类号： G06F13/124 ,  G06F11/349 ,  G06F11/3409 ,  G06F2201/88 ,  G06F2201/885

摘要： A storage controller comprising a storage device adapter, a channel adapter, a cache memory, a control memory, and a plurality of buses connecting therebetween. The channel adapter communicates with a processor and processes input/output requests issued by the processor. The storage device adapter controls a storage device and data transfer between the storage device and the cache memory. The channel adapter and the storage device adapter exchanges control information via the control memory. The buses are used to transfer the data and the control information between the cache memory and the control memory, and the channel adapter and the storage device adapter. The controller also comprises bus load estimating means and bus mode selecting means. The bus load estimating means estimates bus load characteristics as an index based on the amount of data transfer during sequential access to the storage device. The bus mode selecting means determines a bus mode of bus utilization based on the index. Each of the channel adapter and the storage device adapter has bus access means for accessing the buses in accordance with the bus mode selected by the bus mode selecting means.

摘要翻译： 存储控制器，包括存储设备适配器，信道适配器，高速缓冲存储器，控制存储器以及连接在它们之间的多个总线。 信道适配器与处理器通信并处理由处理器发出的输入/输出请求。 存储设备适配器控制存储设备和存储设备与高速缓冲存储器之间的数据传输。 通道适配器和存储设备适配器通过控制存储器交换控制信息。 总线用于将数据和控制信息传输到缓存存储器和控制存储器之间，以及通道适配器和存储设备适配器。 控制器还包括总线负载估计装置和总线模式选择装置。 总线负载估计装置基于在顺序访问存储设备期间的数据传输量来估计总线负载特性作为索引。 总线模式选择装置根据该索引确定总线利用的总线模式。 每个通道适配器和存储设备适配器具有总线访问装置，用于根据由总线模式选择装置选择的总线模式访问总线。