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    Data processor and control circuit for inserting/extracting data to/from an optional byte position of a register
    45.
    发明授权
    Data processor and control circuit for inserting/extracting data to/from an optional byte position of a register 失效
    数据处理器和控制电路，用于从寄存器的可选字节位置插入/提取数据

    公开(公告)号：US5669012A

    公开(公告)日：1997-09-16

    申请号：US720455

    申请日：1996-09-30

    申请人： Toru Shimizu ,  Shunichi Iwata ,  Toshio Doi ,  Shigeo Mizugaki

    发明人： Toru Shimizu ,  Shunichi Iwata ,  Toshio Doi ,  Shigeo Mizugaki

    IPC分类号： G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/308 ,  G06F9/315 ,  G06F9/34 ,  G06F9/35

    CPC分类号： G06F9/30018 ,  G06F9/30032 ,  G06F9/30167

    摘要： A data processor being provided with a microdecoder which decodes instruction codes comprising two operation code parts, a source operand specifying part and a destination operand specifying part, wherein an optional bit area of source data (a register of a general register file or a memory) is inserted in an optional bit area (determined by the value of the first operation code part) of a destination register according to the decoding result, and an optional bit area (determined by the value of the second operation code part) of a source register is extracted and stored in an optional bit area of destination (a register of the general register file or the memory), thereby making it possible to "process the insertion and extraction operations to and from optional byte positions of registers" at a high speed with short instruction code size.

    摘要翻译： 一种数据处理器，其具有对包括两个操作码部分的指令代码，源操作数指定部分和目的地操作数指定部分进行解码的微解码器，其中源数据的可选位区（通用寄存器文件或存储器的寄存器） 根据解码结果插入到目的地寄存器的可选位区域（由第一操作码部分的值确定）和源寄存器的可选位区域（由第二操作码部分的值确定） 被提取并存储在目的地的可选位区（通用寄存器文件或存储器的寄存器）中，从而使得可以以高速“处理到寄存器的可选字节位置的插入和提取操作”成为可能， 短指令代码大小。

    Data processor and read control circuit, write control circuit therefor
    46.
    发明授权
    Data processor and read control circuit, write control circuit therefor 失效
    数据处理器和读控制电路，写控制电路

    公开(公告)号：US5499380A

    公开(公告)日：1996-03-12

    申请号：US245263

    申请日：1994-05-18

    申请人： Shunichi Iwata ,  Toru Shimizu

    发明人： Shunichi Iwata ,  Toru Shimizu

    IPC分类号： G06F12/04 ,  G06F9/312 ,  G06F9/315 ,  G06F12/08

    CPC分类号： G06F9/30043 ,  G06F9/30032 ,  G06F9/3816 ,  G06F12/04

    摘要： A shift circuit 213 used in arithmetic operations is provided with the shift width generating circuit 217 which generates a shift width data from lower bits of an access address and an access size, and a circuit is provided to generated data comprising the first select output circuit 214, the third select output circuit 216 and the like which generate a data by merging byte by byte selected from either an output of the shift circuit 213 or a value of a register of a register file 210 according to the combination of the lower bits of the access address and the access size. It is possible to align the data in the shift circuit 213 which is provided for the purpose of arithmetic operations, and exclusive alignment circuit is made unnecessary thereby enabling it to reduce the amount of hardware.

    摘要翻译： 在算术运算中使用的移位电路213设置有移位宽度产生电路217，其从存取地址和访问大小的较低位产生移位宽度数据，并且电路被提供给包括第一选择输出电路214的生成数据 ，第三选择输出电路216等，其通过从移位电路213的输出或从寄存器文件210的寄存器的值中逐个字节合并而生成数据， 访问地址和访问大小。 可以对用于算术运算的目的而设置的移位电路213中的数据进行对准，并且不需要专用对准电路，从而能够减少硬件的数量。

    System having status update controller for determining which one of parallel operation results of execution units is allowed to set conditions of shared processor status word
    47.
    发明授权
    System having status update controller for determining which one of parallel operation results of execution units is allowed to set conditions of shared processor status word 失效
    具有用于确定执行单元的并行操作结果中的哪一个被允许设置共享处理器状态字的条件的状态更新控制器的系统

    公开(公告)号：US5313644A

    公开(公告)日：1994-05-17

    申请号：US619852

    申请日：1990-11-28

    申请人： Masahito Matsuo ,  Toru Shimizu

    发明人： Masahito Matsuo ,  Toru Shimizu

    IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/06

    CPC分类号： G06F9/30094 ,  G06F9/30101 ,  G06F9/3885

    摘要： A data processing system which is provided with a plurality of operation units and a function which executes a plurality of instructions in parallel by each of these plurality of operation units, respectively, wherein operation results executed by these plurality of operation units are reflected on flags which are included in a processor status word (PSW), thereby, those plurality of instructions are executed in parallel in the respective different operation units, and at that time, results of operation processing of the respective instructions are reflected on the flags included in the PSW, then, the flags can be updated by simple control, and the operation results executed by those plurality of operation units are reflected on the flags included in the PSW according to the order of execution of the instructions, thereby, those plurality of instructions are executed in parallel by the respective different operation units, and at that time, the results of operation processing of the respective instructions are reflected on the flags included in the PSW according to the order of execution of the instructions, whereby enabling to realize the high speed operation without providing such complicated processing as temporarily saving information for reflecting the results of operation processing on the flags until processing of the preceding instructions is finished.

    摘要翻译： 一种数据处理系统，其具有多个操作单元和分别执行多个操作单元中的每一个并行执行多个指令的功能，其中由这些多个操作单元执行的操作结果被反映在 被包括在处理器状态字（PSW）中，从而在各个不同的操作单元中并行地执行那些多个指令，并且此时各个指令的操作处理结果被反映在包括在PSW中的标志 ，则可以通过简单的控制来更新标志，并且由多个操作单元执行的操作结果根据指令的执行顺序反映在包含在PSW中的标志上，从而执行这些多个指令 并行地由各自的不同的操作单元组成，并且当时的操作处理结果 观察指令根据指令执行顺序反映在PSW中包含的标志上，从而能够实现高速操作，而不需要提供诸如暂时保存用于反映标志上的操作处理结果的信息的复杂处理，直到处理 的上述说明完成。

    Microprocessor with pipeline system having exception processing features
    48.
    发明授权
    Microprocessor with pipeline system having exception processing features 失效
    具有管道系统的微处理器具有异常处理功能

    公开(公告)号：US5297263A

    公开(公告)日：1994-03-22

    申请号：US871598

    申请日：1992-04-17

    申请人： Akira Ohtsuka ,  Toru Shimizu

    发明人： Akira Ohtsuka ,  Toru Shimizu

    IPC分类号： G06F9/38 ,  G06F11/00

    CPC分类号： G06F9/3865 ,  G06F9/3867

    摘要： A method and apparatus for processing exceptions in a microprocessor having a plurality of pipelined stages. The method comprises the steps of generating an exception processing code at a given stage to indicate the occurrence of an exception at the given stage; temporarily stopping processing at the given stage; transferring the exception processing code to a special stage; decoding said exception processing code at the special stage; and causing the pipeline to execute exception processing when the exception processing code is decoded at the special stage. Using the invention, the microprocessor can avoid much of the delay and complexity resulting from using an external circuit to control exception processing and can cope with the occurrence of an exception at any stage without prematurely cancelling or reexecuting processing steps. The invention is simplified in both hardware and software, and can easily cope with expansion of the number of stages.

    摘要翻译： 一种在具有多个流水线阶段的微处理器中处理异常的方法和装置。 该方法包括以下步骤：在给定阶段产生异常处理代码，以指示给定阶段发生异常; 在给定阶段临时停止处理; 将异常处理代码转移到特殊阶段; 在特殊阶段解码所述异常处理代码; 并且在异常处理代码在特殊阶段被解码时使得流水线执行异常处理。 使用本发明，微处理器可以避免使用外部电路来控制异常处理的大部分延迟和复杂性，并且可以在任何阶段处理异常的发生，而不会过早地取消或重新执行处理步骤。 本发明在硬件和软件方面都被简化，并且可以容易地应付阶段的扩展。

    High speed data processing unit using a shift operation
    50.
    发明授权
    High speed data processing unit using a shift operation 失效
    高速数据处理单元采用移位操作

    公开(公告)号：US4872128A

    公开(公告)日：1989-10-03

    申请号：US156766

    申请日：1988-02-17

    申请人： Toru Shimizu

    发明人： Toru Shimizu

    IPC分类号： G06F7/00 ,  G06F5/01 ,  G06F7/57 ,  G06F7/76

    CPC分类号： G06F7/57 ,  G06F5/01

    摘要： A data processing unit includes a data register, a shift width register, an absolute value generator, a shift direction control circuit, and a shifter. The shifter is responsive to an absolute value of shift width data in the shift width register and a sign of the shift width data to decide the number of shift positions and the shift direction of data in the data register for performing a shift operation.

    摘要翻译： 数据处理单元包括数据寄存器，移位宽度寄存器，绝对值生成器，移位方向控制电路和移位器。 移位器响应于移位宽度寄存器中的移位宽度数据的绝对值和移位宽度数据的符号，以决定用于执行移位操作的数据寄存器中的移位位置数和移位方向。