公开(公告)号：US5543647A

公开(公告)日：1996-08-06

申请号：US339200

申请日：1994-11-10

申请人： Maiko Kobayashi ,  Takashi Kuroi

发明人： Maiko Kobayashi ,  Takashi Kuroi

IPC分类号： H01L21/76 ,  H01L21/265 ,  H01L21/762 ,  H01L29/10 ,  H01L29/76

CPC分类号： H01L29/1083 ,  H01L21/762

摘要： A semiconductor device in which ability for isolating elements from each other can be improved and increase in substrate constant and junction capacitance can be suppressed, is disclosed. An impurity layer for improving the ability for isolating elements is positioned only immediately below an isolating insulating film. An impurity layer for adjusting substrate constant and junction capacitance is formed through independent steps from the impurity layer for improving the isolating ability.

摘要翻译： 公开了能够提高彼此隔离元件的能力的半导体器件，并且可以抑制衬底常数和结电容的增加。 用于提高隔离元件的能力的杂质层位于隔离绝缘膜的正下方。 用于调整衬底常数的杂质层和结电容通过与杂质层的独立步骤形成，以提高隔离能力。

公开(公告)号：US5488245A

公开(公告)日：1996-01-30

申请号：US318482

申请日：1994-10-05

申请人： Masahiro Shimizu ,  Masayoshi Shirahata ,  Takashi Kuroi ,  Takehisa Yamaguchi

发明人： Masahiro Shimizu ,  Masayoshi Shirahata ,  Takashi Kuroi ,  Takehisa Yamaguchi

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7883

摘要： A semiconductor memory device and a manufacturing method of the same can effectively prevent deterioration of endurance characteristic which may occur in a data erasing operation, and a drain disturb phenomenon which may occur in a data writing operation. In the semiconductor memory device, an N-type impurity layer 3 is formed on a main surface of a P-type silicon substrate 1 located in a channel region. Thereby, a high electric field is not applied to a boundary region between the N-type impurity layer 3 and an N-type source diffusion region 10 during erasing of data, so that generation of interband tunneling in this region is effectively prevented. Also in this semiconductor memory device, the drain diffusion region 9 has an offset structure in which no portion thereof overlaps the floating gate electrode 5. Therefore, an electric field, which is generated across the floating gate electrode 5 and the drain diffusion region 9 in an unselected cell during writing of data, is weakened, as compared with the prior art, and the drain disturb phenomenon due to F-N tunneling is effectively prevented.

摘要翻译： 半导体存储器件及其制造方法可以有效地防止在数据擦除操作中可能发生的耐久特性的劣化，以及在数据写入操作中可能发生的漏极干扰现象。 在半导体存储器件中，在位于沟道区域中的P型硅衬底1的主表面上形成N型杂质层3。 因此，在擦除数据期间，不向N型杂质层3和N型源极扩散区域10之间的边界区域施加高电场，从而有效地防止了在该区域产生带间隧穿。 另外，在该半导体存储器件中，漏极扩散区域9具有偏移结构，其中没有任何部分与浮置栅极电极5重叠。因此，在浮置栅极电极5和漏极扩散区域9两端产生的电场 与现有技术相比，写入数据期间的未选择的单元被削弱，并且有效地防止了由于FN隧穿引起的漏极干扰现象。

公开(公告)号：US5341022A

公开(公告)日：1994-08-23

申请号：US31988

申请日：1993-03-16

申请人： Takashi Kuroi ,  Shigeru Kusunoki

发明人： Takashi Kuroi ,  Shigeru Kusunoki

IPC分类号： H01L21/265 ,  H01L21/322 ,  H01L21/331 ,  H01L29/08 ,  H01L29/73 ,  H01L29/732 ,  H01L29/32

CPC分类号： H01L29/66272 ,  H01L21/3221 ,  H01L29/0821 ,  Y10S148/01 ,  Y10S148/086 ,  Y10S257/928

摘要： A semiconductor device having a reduced leakage current is fabricated in a short time at a low cost with excellent controllability. A buried layer (20) which includes a principal buried layer (21) of high ion concentration containing secondary defects (22) sandwiched between secondary buried layers (3a, 3b) of low ion concentration from upper and lower directions is formed on a semiconductor substrate (1). The secondary defects (22) have stable gettering effects for reducing defects caused during formation of a transistor (200) and contamination by heavy metals. Further, the secondary buried layers (3a, 3b) prevent depletion layers from reaching the secondary defects (22). The semiconductor device can be formed in a short time since no epitaxial growth is employed.

摘要翻译： 在短时间内以低成本制造具有减小的漏电流的半导体器件，具有优异的可控性。 在半导体衬底上形成埋设层（20），该掩埋层（20）包括高离子浓度的主要埋置层（21），其含有从上下方向上的低离子浓度的二次掩埋层（3a，3b）夹入的二次缺陷（22） （1）。 二次缺陷（22）具有稳定的吸气效应，可减少晶体管（200）形成过程中产生的缺陷和重金属污染。 此外，二次埋层（3a，3b）防止耗尽层达到二次缺陷（22）。 半导体器件可以在短时间内形成，因为不使用外延生长。

公开(公告)号：US06521527B1

公开(公告)日：2003-02-18

申请号：US09922663

申请日：2001-08-07

申请人： Takashi Kuroi ,  Shuichi Ueno ,  Hidekazu Oda ,  Satoshi Shimizu

发明人： Takashi Kuroi ,  Shuichi Ueno ,  Hidekazu Oda ,  Satoshi Shimizu

IPC分类号： H01L2144

CPC分类号： H01L29/0847 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66765 ,  H01L29/7833 ,  H01L29/78618

摘要： Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P+-type gate electrode which are formed on a P-type silicon substrate are doped with nitrogen.

摘要翻译： 获得的是能够防止栅电极中所含杂质扩散的半导体器件及其制造方法。 在该半导体器件中，形成在P型硅衬底上的栅极氧化膜和P +型栅极掺杂有氮。

公开(公告)号：US5956600A

公开(公告)日：1999-09-21

申请号：US792727

申请日：1997-01-31

申请人： Takashi Kuroi ,  Maiko Kobayashi

发明人： Takashi Kuroi ,  Maiko Kobayashi

IPC分类号： H01L21/316 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/318 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76205

摘要： An element isolation region is formed in a silicon substrate by initially depositing an insulating film and first nitride film thereon, forming an opening therethrough exposing the substrate, and etching the substrate to form a groove. A polysilicon film and second nitride film are successively deposited, and the second nitride film is anisotropically etched to expose the polysilicon film at the bottom of the groove. The silicon substrate is then thermally oxidized using the first and second nitride films as a mask to form the element isolation region. In other embodiments, an oxide film is formed at the bottom of the groove prior or subsequent to deposition of the polysilicon film.

摘要翻译： 通过在其上初始沉积绝缘膜和第一氮化物膜，形成在硅衬底中的元件隔离区域，形成通过其暴露衬底的开口，并蚀刻衬底以形成沟槽。 依次沉积多晶硅膜和第二氮化物膜，并且第二氮化物膜被各向异性地蚀刻以暴露沟槽底部的多晶硅膜。 然后使用第一和第二氮化物膜作为掩模将硅衬底热氧化以形成元件隔离区。 在其他实施例中，在沉积多晶硅膜之前或之后，在凹槽的底部形成氧化物膜。

公开(公告)号：US5683923A

公开(公告)日：1997-11-04

申请号：US480701

申请日：1995-06-07

申请人： Masahiro Shimizu ,  Masayoshi Shirahata ,  Takashi Kuroi ,  Takehisa Yamaguchi

发明人： Masahiro Shimizu ,  Masayoshi Shirahata ,  Takashi Kuroi ,  Takehisa Yamaguchi

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7883

摘要： A semiconductor memory device and a manufacturing method of the same can effectively prevent deterioration of endurance characteristic which may occur in a data erasing operation, and a drain disturb phenomenon which may occur in a data writing operation. In the semiconductor memory device, an N-type impurity layer 3 is formed on a main surface of a P-type silicon substrate 1 located in a channel region. Thereby, a high electric field is not applied to a boundary region between the N-type impurity layer 3 and an N-type source diffusion region 10 during erasing of data, so that generation of interband tunneling in this region is effectively prevented. Also in this semiconductor memory device, the drain diffusion region 9 has an offset structure in which no portion thereof overlaps the floating gate electrode 5. Therefore, an electric field, which is generated across the floating gate electrode 5 and the drain diffusion region 9 in an unselected cell during writing of data, is weakened, as compared with the prior art, and the drain disturb phenomenon due to F-N tunneling is effectively prevented.

摘要翻译： 半导体存储器件及其制造方法可以有效地防止在数据擦除操作中可能发生的耐久特性的劣化，以及在数据写入操作中可能发生的漏极干扰现象。 在半导体存储器件中，在位于沟道区域中的P型硅衬底1的主表面上形成N型杂质层3。 因此，在擦除数据期间，不向N型杂质层3和N型源极扩散区域10之间的边界区域施加高电场，从而有效地防止了在该区域产生带间隧穿。 另外，在该半导体存储器件中，漏极扩散区域9具有偏移结构，其中没有任何部分与浮置栅极电极5重叠。因此，在浮置栅极电极5和漏极扩散区域9两端产生的电场 与现有技术相比，写入数据期间的未选择的单元被削弱，并且有效地防止了由于FN隧穿引起的漏极干扰现象。

公开(公告)号：US5446305A

公开(公告)日：1995-08-29

申请号：US240282

申请日：1994-05-09

申请人： Shigeki Komori ,  Takashi Kuroi ,  Masahide Inuishi

发明人： Shigeki Komori ,  Takashi Kuroi ,  Masahide Inuishi

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L27/02 ,  H01L29/70

CPC分类号： H01L27/0921 ,  H01L27/10805 ,  Y10S148/085

摘要： A semiconductor device includes a p-type silicon substrate, a first well of p-type formed in a major surface of the silicon substrate, and a second well of n-type formed close to the first well in the major surface of the silicon substrate. A third well of p-type is formed inside the second well and, furthermore, a conductive layer including p-type impurities of higher concentration than that of the first well is formed as extending immediately below both the first well and the second well. In accordance with this structure, even if minority carriers are injected, they recombine and disappear in the conductive layer, so that the implantation of the carriers into the first well is prevented. As a result, various disadvantageous phenomena due to the injection of the minority carriers are prevented and a semiconductor device having a stable device characteristic and high integration density is provided.

摘要翻译： 半导体器件包括p型硅衬底，形成在硅衬底的主表面中的p型第一阱和在硅衬底的主表面中靠近第一阱形成的n型第二阱 。 在第二阱内形成第三阱p型，此外，形成包含比第一阱高的浓度的p型杂质的导电层，直接在第一阱和第二阱的正下方延伸。 根据该结构，即使注入少量载流子，它们在导电层中复合并消失，从而防止载流子注入到第一阱中。 结果，防止了由于少数载流子的注入引起的各种不利现象，并且提供了具有稳定的器件特性和高集成度的半导体器件。

公开(公告)号：US06232187B1

公开(公告)日：2001-05-15

申请号：US09280992

申请日：1999-03-30

申请人： Takashi Kuroi ,  Hirokazu Sayama

发明人： Takashi Kuroi ,  Hirokazu Sayama

IPC分类号： H01L21336

CPC分类号： H01L29/512 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28202 ,  H01L29/511 ,  H01L29/518

摘要： A highly reliable semiconductor device and a manufacturing method thereof are provided, without lowering the mobility of carriers, by increasing the nitrogen concentration of part of a gate insulating film. Nitrogen containing regions containing nitrogen are provided on both end portions of a gate insulating film which is formed into a uniform thickness.

摘要翻译： 提供了一种高度可靠的半导体器件及其制造方法，通过增加部分栅极绝缘膜的氮浓度，而不降低载流子的迁移率。 在形成为均匀厚度的栅极绝缘膜的两端部设置含有氮的含氮区域。

公开(公告)号：US5950098A

公开(公告)日：1999-09-07

申请号：US911979

申请日：1997-08-15

申请人： Hidekazu Oda ,  Takashi Kuroi

发明人： Hidekazu Oda ,  Takashi Kuroi

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L21/425

CPC分类号： H01L29/66575 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/456 ,  H01L29/4933

摘要： To form a silicide layer excellent in flatness, uniform in film thickness, and less in junction leak, by destroying the natural oxide film which adversely affects a formation of silicide layer of cobalt or nickel. A cobalt layer (7) is formed in a film thickness of 20 nm or less on an electrode layer (4A) of a gate electrode (4) and on source/drain diffusion layers (1, 2), and a nitrogen (8) is injected by the ion implantation at a density of about 1E15/cm.sup.3 with an injection energy of 10 keV or more. At this time, the nitrogens (8) destroy the natural oxide film existing in the interface of the cobalt layer (7) and electrode layer (4A), and in the interface of the cobalt layer (7) and the source/drain diffusion layers (1, 2), and distribute deeply into the electrode layer (4A) and the source/drain diffusion layers (1, 2). Later, by a silicide forming reaction of cobalt, a silicide layer (6) is formed. Since the natural oxide film does not exist, the silicide forming reaction proceeds uniformly. Instead of the nitrogen (8), fluorine or silicon may be also used.

摘要翻译： 通过破坏对钴或镍的硅化物层的形成有不利影响的自然氧化膜，形成平坦度优异，膜厚均匀，并且漏点较少的硅化物层。 在栅电极（4）的电极层（4A）和源/漏扩散层（1,2）上形成厚度为20nm以下的钴层（7），氮（8） 通过离子注入以约1E15 / cm3的密度注入，注入能量为10keV以上。 此时，氮（8）破坏存在于钴层（7）和电极层（4A）的界面中的自然氧化膜，并且在钴层（7）和源极/漏极扩散层 （1,2），并且深深地分布到电极层（4A）和源极/漏极扩散层（1,2）中。 然后，通过钴的硅化物形成反应，形成硅化物层（6）。 由于天然氧化物膜不存在，所以硅化物形成反应均匀地进行。 代替氮（8），也可以使用氟或硅。

公开(公告)号：US06577021B2

公开(公告)日：2003-06-10

申请号：US10096728

申请日：2002-03-14

申请人： Chikayoshi Morishima ,  Yoshinori Okumura ,  Takashi Kuroi

发明人： Chikayoshi Morishima ,  Yoshinori Okumura ,  Takashi Kuroi

IPC分类号： H01L2711

CPC分类号： H01L27/1104 ,  Y10S257/904

摘要： An SRAM of the present invention comprises a plurality of memory cells, which are formed over a plurality of wells, which store data and which do not have a well contact region for fixing the potential of the wells, and a plurality of well contact cells for fixing the potential of the wells that are formed over the plurality of wells so as to adjoin the memory cells, wherein the areas of the memory cells and the areas of the well contact cells are equal.