公开(公告)号：US11222680B2

公开(公告)日：2022-01-11

申请号：US17097738

申请日：2020-11-13

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Corrado Villa

IPC: G11C11/22 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented in a plane parallel to rows of a memory array or columns of the memory array, or both. The segmented plate may be employed instead of a single plate for the array. The one or more plate portions may be energized during access operations of a ferroelectric cell in order to create a voltage different across the cell or to facilitate changing the charge of the cell. Each of the plate portions may include one or more memory cells. The memory cells on a plate portion may be read from or written to after the plate portion is activated by a plate driver.

公开(公告)号：US20210335407A1

公开(公告)日：2021-10-28

申请号：US17231704

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Andrea Martinelli

IPC: G11C11/22 ,  G06F3/06

Abstract: Methods, systems, and devices for activity-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include determining a quantity of access operations performed on a set of sections of a memory device, selecting at least one of the sections for a voltage adjustment operation based on the determined quantity of access operations, and performing the voltage adjustment operation on the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.

公开(公告)号：US11158673B2

公开(公告)日：2021-10-26

申请号：US16771658

申请日：2019-12-18

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Corrado Villa ,  Paolo Tessariol

IPC: G11C16/04 ,  H01L27/24 ,  G11C8/08

Abstract: A vertical 3D memory device may comprise: a substrate including a plurality of conductive contacts each coupled with a respective one of a plurality of digit lines; a plurality of word line plates separated from one another with respective dielectric layers on the substrate, the plurality of word line plates including at least a first set of word lines separated from at least a second set of word lines with a dielectric material extending in a serpentine shape and at least a third set of word lines separated from at least a fourth set of word lines with a dielectric material extending in a serpentine shape; at least one separation layer separating the first set of word lines and the second set of word lines from the third set of word lines and the fourth set of word lines, wherein the at least one separation layer is parallel to both a digit line and a word line; and a plurality of storage elements each formed in a respective one of a plurality of recesses such that a respective storage element is surrounded by a respective word line, a respective digit line, respective dielectric layers, and a conformal material formed on a sidewall of a word line facing a digit line.

公开(公告)号：US20210134341A1

公开(公告)日：2021-05-06

申请号：US17097738

申请日：2020-11-13

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Corrado Villa

IPC: G11C11/22 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented in a plane parallel to rows of a memory array or columns of the memory array, or both. The segmented plate may be employed instead of a single plate for the array. The one or more plate portions may be energized during access operations of a ferroelectric cell in order to create a voltage different across the cell or to facilitate changing the charge of the cell. Each of the plate portions may include one or more memory cells. The memory cells on a plate portion may be read from or written to after the plate portion is activated by a plate driver.

公开(公告)号：US20210020205A1

公开(公告)日：2021-01-21

申请号：US17062202

申请日：2020-10-02

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Corrado Villa

IPC: G11C5/14 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

公开(公告)号：US20190341083A1

公开(公告)日：2019-11-07

申请号：US16513115

申请日：2019-07-16

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Corrado Villa

IPC: G11C5/14 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

公开(公告)号：US20180033467A1

公开(公告)日：2018-02-01

申请号：US15223753

申请日：2016-07-29

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa

IPC: G11C7/10 ,  G11C8/16 ,  G06F3/06

Abstract: Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.

公开(公告)号：US20160351263A1

公开(公告)日：2016-12-01

申请号：US15170609

申请日：2016-06-01

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Corrado Villa

IPC: G11C16/10 ,  G11C13/00 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3459 ,  G11C2213/79

Abstract: The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.

公开(公告)号：US12086421B2

公开(公告)日：2024-09-10

申请号：US17684112

申请日：2022-03-01

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Corrado Villa ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0679

Abstract: A method to perform data scrub operations by operating a memory device, the memory device comprising a main memory, an internal Error Correction Code (ECC) engine and a scrub memory. The method comprising: receiving a read command; accessing, based on the receiving the read command, a location in the main memory to read data at the location; error correcting data read during the accessing; and storing at the scrub memory information of the location based at least in part on the correcting the data meeting or exceeding an ECC threshold.

公开(公告)号：US12051463B2

公开(公告)日：2024-07-30

申请号：US17864004

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Jeffrey E. Koelling ,  Hari Giduturi ,  Riccardo Muzzetto ,  Corrado Villa

IPC: G11C13/00

CPC classification number: G11C13/0026 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0033

Abstract: Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.