公开(公告)号：US20130001799A1

公开(公告)日：2013-01-03

申请号：US13608456

申请日：2012-09-10

申请人： Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L23/498

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/525 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68359 ,  H01L2224/13022 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/14181 ,  H01L2924/01019 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.

摘要翻译： 提供了用于堆叠管芯配置的多层互连结构。 在半导体衬底中形成贯通衬底通孔。 将半导体衬底的背面变薄以暴露通过衬底的通孔。 在半导体衬底的背面和贯通衬底通孔的暴露部分之后形成隔离膜。 第一导电元件被形成为电耦合到贯穿衬底通孔中的相应通孔并且在隔离膜上延伸。 可以形成一个或多个附加层的隔离膜和导电元件，其中诸如焊球的连接元件电耦合到最上面的导电元件。

公开(公告)号：US06544882B1

公开(公告)日：2003-04-08

申请号：US09482049

申请日：2000-01-13

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L21302

CPC分类号： H01L21/7685 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/31629 ,  H01L21/76858 ,  Y10S438/952

摘要： In the fabrication of integrated circuits containing multilevel structures of FSG (F-doped SiO2) dielectric layers and aluminum-copper-TiN layers, superior adhesion between the FSG and aluminum-copper-TiN is achieved by subjecting the aluminum-copper-TiN layer to a plasma containing N2 and H2 or N2 and NH3 prior to deposition of the FSG layer. It is believed that the plasma treatment converts unreacted Ti within the TiN layer to TiN and, also, stuffs grain boundaries within the TiN layer with N2. The result is a void-free TiN layer which is impervious to F atoms residing in the FSG layer.

摘要翻译： 在包含FSG（F掺杂SiO 2）电介质层和铝 - 铜-TiN层的多层结构的集成电路的制造中，FSG和铝 - 铜-TiN层之间的优异的附着力通过将铝 - 铜-TiN层 在沉积FSG层之前，含有N 2和H 2或N 2和NH 3的等离子体。 据信等离子体处理将TiN层内的未反应的Ti转化为TiN，并且还用N 2将TiN层内的晶界填充。 结果是无孔的TiN层，其不存在存在于FSG层中的F原子。

公开(公告)号：US06500749B1

公开(公告)日：2002-12-31

申请号：US09810123

申请日：2001-03-19

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L214763

CPC分类号： H01L23/53238 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to fabricate a metal via structure having improved electromigration resistance, comprising the following steps. A semiconductor structure having an exposed metal interconnect structure therein is provided. The metal interconnect structure including a metal via portion. A capping layer is formed over the metal interconnect structure. A via pattern structure is formed over the capping layer. The via pattern structure having a via pattern hole aligned with the metal via portion of the metal interconnect structure. Ions are implanted through the via pattern hole into the metal via portion, and any portion of the metal interconnect structure above the metal via portion. Whereby the metal via portion and the portion of the metal interconnect structure above the metal via portion have improved electromigration resistance.

摘要翻译： 一种制造具有改善的电迁移阻力的金属孔结构的方法，包括以下步骤。 提供其中具有暴露的金属互连结构的半导体结构。 金属互连结构包括金属通孔部分。 在金属互连结构上形成覆盖层。 在覆盖层上形成通孔图案结构。 通孔图案结构具有与金属互连结构的金属通孔部分对准的通孔图形孔。 离子通过通孔图案孔注入金属通孔部分中，并且金属互连结构的任何部分在金属通孔部分上方。 金属通孔部分和金属通孔部分上方的金属互连结构的部分具有改善的电迁移阻力。

公开(公告)号：US06492269B1

公开(公告)日：2002-12-10

申请号：US09755570

申请日：2001-01-08

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu ,  Ching-Hua Hsieh

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu ,  Ching-Hua Hsieh

IPC分类号： H01L2144

CPC分类号： H01L21/2885 ,  H01L21/76877 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention relates to a method of fabrication for metal wiring used in semiconductor integrated circuit devices, and more specifically, to a copper plating method, whereby the wafer edge alignment marks for subsequent processing steps are protected from being covered by copper deposition by two methods: the first method being that of forming alignment mark shields at the wafer's edge, thus preventing both barrier and copper seed layers from being deposited in those regions; the second method being that of forming small pad-like extrusions at the contact ring of the copper plating fixture, thus preventing copper plating at the contact points. In the first method, an alignment mark shield Is utilized to cover the alignment mark areas, near the edge of the wafer, with a mechanical shield. This shield protects the alignment mark regions from film deposition during the sputter deposition steps of barrier and copper seed layers. The alignment marks are left without a copper seed layer, hence preventing copper deposition in these regions during copper electroplating. In the second method, the alignment mark areas, near the edge of the wafer, are protected from copper electroplating deposition by use of small pad-like extrusions positioned at copper plating contact ring. The pad-like extrusion is part of the contact ring and prevents copper buildup and deposition on the alignment mark.

摘要翻译： 本发明涉及一种用于半导体集成电路器件的金属布线的制造方法，更具体地说，涉及一种镀铜方法，由此通过两种方法保护用于后续处理步骤的晶片边缘对准标记不被铜沉积覆盖： 第一种方法是在晶片边缘处形成对准标记屏蔽，从而防止屏障和铜种子层沉积在那些区域中; 第二种方法是在镀铜夹具的接触环处形成小的垫状挤压件，从而防止接触点处的镀铜。 在第一种方法中，使用对准标记屏蔽来利用机械屏蔽覆盖晶片边缘附近的对准标记区域。 在屏障和铜种子层的溅射沉积步骤期间，该屏蔽件保护对准标记区域免受膜沉积。 留下对准标记没有铜种子层，因此在铜电镀期间防止这些区域中的铜沉积。 在第二种方法中，通过使用位于铜电镀接触环的小的垫状突出部，在晶片的边缘附近的对准标记区域被保护以避免铜电镀沉积。 垫状挤出物是接触环的一部分，可防止铜对准标记上的积累和沉积。

公开(公告)号：US06372645B1

公开(公告)日：2002-04-16

申请号：US09439367

申请日：1999-11-15

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu ,  Shih-Chi Lin ,  Ming-Jer Lee ,  Ying-Lang Wang ,  Yu-Ku Lin

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu ,  Shih-Chi Lin ,  Ming-Jer Lee ,  Ying-Lang Wang ,  Yu-Ku Lin

IPC分类号： H01L2144

CPC分类号： H01L21/76838 ,  H01L21/32051

摘要： In the first option of the present invention, a semiconductor structure is provided and an overlying titanium nitride barrier layer is deposited thereon at about 100° C. At least Al and Cu is sputtered over the titanium nitride barrier layer from about 270 to 300° C. to form an Al—Cu alloy containing metal layer. The sputtered Al—Cu alloy containing metal layer is promptly cooled at a cooling rate greater than about 100° C./minute to a temperature below 200° C. to form a Al—Cu alloy containing metal layer having minimal CuAl2 grain growth. The semiconductor structure is removed from the cooling chamber and the semiconductor structure is processed further below 200° C. to form semiconductor device precursors. In the second option of the present invention, a semiconductor structure having an overlying barrier layer is provided. At least Al and Cu is sputtered over the barrier layer at a first temperature to form an Al—Cu alloy containing metal layer having CuAl2 grains of a first average size. The semiconductor structure is processed and then heated to a second temperature to dissolve the CuAl2 grains of a first average size then rapidly cooling to a third temperature whereby the CuAl2 grains formed have a second average size within the Al—Cu alloy containing metal layer. The second average size CuAl2 grains being less than the first average size CuAl2 grains.

摘要翻译： 在本发明的第一种选择中，提供了一种半导体结构，并在其上沉积了大约100℃的上覆氮化钛阻挡层。至少Al和Cu溅射在氮化钛阻挡层上约270-300℃ 以形成含有金属层的Al-Cu合金。 将溅射的含有Al-Cu合金的金属层以大于约100℃/分钟的冷却速度迅速冷却到低于200℃的温度，以形成含有最小CuAl 2晶粒生长的金属层的Al-Cu合金。 将半导体结构从冷却室中移除，半导体结构进一步在200℃以下进行处理以形成半导体器件前体。 在本发明的第二个选择中，提供了具有上覆阻挡层的半导体结构。 在第一温度下至少将Al和Cu溅射在阻挡层上，以形成含有具有第一平均尺寸的CuAl 2晶粒的金属层的Al-Cu合金。 将半导体结构加工，然后加热至第二温度以溶解第一平均尺寸的CuAl 2晶粒，然后快速冷却至第三温度，由此形成的CuAl 2晶粒在含有Al-Cu合金的金属层内具有第二平均尺寸。 第二平均尺寸CuAl2晶粒小于第一平均尺寸CuAl2晶粒。

公开(公告)号：US06350688B1

公开(公告)日：2002-02-26

申请号：US09629646

申请日：2000-08-01

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L2144

CPC分类号： H01L21/76886 ,  C25D5/48 ,  C25D5/50 ,  C25D7/123 ,  H01L21/76877

摘要： A new anneal procedure is provided that is applied to copper damascene via interconnects after copper ECP deposition and prior to copper planarization.

摘要翻译： 提供了一种新的退火方法，通过铜ECP沉积之后和铜平坦化之前通过互连应用于铜镶嵌层。

公开(公告)号：US06099701A

公开(公告)日：2000-08-08

申请号：US342034

申请日：1999-06-28

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L23/532 ,  C23C14/34 ,  H01L21/4763

CPC分类号： H01L21/7685 ,  H01L21/76841 ,  H01L23/53223 ,  H01L2924/0002

摘要： A method of manufacturing a Al-Cu line stack comprised of Ti-rich TIN, TiN, Ti-rich TiN, Al-Cu, Ti-rich TiN, TiN layers. A key feature of the invention is the sputtering of the Ti-rich TiN layers and TiN layers in the same Ti sputter chamber by turning off and on the N.sub.2 gas flow. For example, the Ti-rich TiN layer is formed by sputtering Ti with the N.sub.2 gas initially turned off. The overlying TiN layer is sputtered with the N.sub.2 gas turned on and the process stabilizes. The Ti-rich TiN layer is sputtered during a N.sub.2 off step (no N.sub.2 gas flow). The invention's Ti-rich TiN, TiN, Ti-rich TiN, Al-Cu, Ti-rich TiN, TiN layers increase the electromigration resistance.

摘要翻译： 一种由富Ti的TIN，TiN，富Ti的TiN，Al-Cu，富Ti的TiN，TiN层构成的Al-Cu线叠层的制造方法。 本发明的一个关键特征是通过关闭和在N2气流上溅射相同Ti溅射室中的富钛TiN层和TiN层。 例如，通过溅射Ti，最初关闭N 2气体来形成富Ti的TiN层。 上覆的TiN层被溅射，N2气开启，工艺稳定。 在N 2脱氮步骤（无N2气流）下溅镀Ti富Ti Ti层。 本发明的富钛TiN，TiN，富钛TiN，Al-Cu，Ti富TiN，TiN层增加了电迁移率。

公开(公告)号：US6096651A

公开(公告)日：2000-08-01

申请号：US228126

申请日：1999-01-11

申请人： Mei-Yun Wang ,  Chen-Hua Yu ,  Shau-Lin Shue

发明人： Mei-Yun Wang ,  Chen-Hua Yu ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L21/302

CPC分类号： H01L21/76865 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76862

摘要： The problem of key-hole formation during the filling of small diameter via holes has been overcome by means of soft sputtering in argon after the barrier layer is in place. This sputtering step may be used twice--once to widen the mouth of a newly formed via hole, and a second time after the barrier layer is in place, thereby widening the mouth further (as well as removing oxide from the surface of the barrier layer). In an alternate optional embodiment, widening of the via hole mouth may be limited to a single sputtering step after the barrier layer has been laid down. In either case, this is followed by filling of the via hole which occurs without any key-hole formation.

摘要翻译： 通过在阻挡层就位之后的氩气中的软溅射，克服了在小直径通孔填充期间形成孔洞的问题。 该溅射步骤可以使用两次一次来加宽新形成的通孔的口，并且在阻挡层就位之后的第二次，从而进一步扩大口（以及从阻挡层的表面去除氧化物） ）。 在替代的可选实施例中，通孔口的加宽可以在阻挡层被铺设之后被限制到单个溅射步骤。 在任一种情况下，随后填充通孔而没有任何键孔形成。

公开(公告)号：US20120190191A1

公开(公告)日：2012-07-26

申请号：US13440704

申请日：2012-04-05

申请人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

发明人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

IPC分类号： H01L21/768

CPC分类号： H01L21/76849 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76865 ,  H01L21/76883

摘要： An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.

摘要翻译： 集成电路包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的第一开口，第一开口中的第一扩散阻挡层，覆盖第一开口中的低k电介质层 开口，其中所述第一扩散阻挡层具有连接到侧壁部分的底部，并且其中所述侧壁部分具有靠近所述低k电介质层的顶表面的顶表面。 集成电路还包括填充第一开口的导电线，其中导电线具有比扩散阻挡层的侧壁部分的顶表面低的顶表面，以及导电线上的金属盖，并且仅在直接在 导线。

公开(公告)号：US08623760B2

公开(公告)日：2014-01-07

申请号：US13440704

申请日：2012-04-05

申请人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

发明人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

IPC分类号： H01L21/768

CPC分类号： H01L21/76849 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76865 ,  H01L21/76883

摘要： An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.

摘要翻译： 集成电路包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的第一开口，第一开口中的第一扩散阻挡层，覆盖第一开口中的低k电介质层 开口，其中所述第一扩散阻挡层具有连接到侧壁部分的底部，并且其中所述侧壁部分具有靠近所述低k电介质层的顶表面的顶表面。 集成电路还包括填充第一开口的导电线，其中导电线具有比扩散阻挡层的侧壁部分的顶表面低的顶表面，以及导电线上的金属盖，并且仅在直接在 导线。