公开(公告)号：US20070287294A1

公开(公告)日：2007-12-13

申请号：US11448713

申请日：2006-06-08

申请人： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Shau-Lin Shue

发明人： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Shau-Lin Shue

IPC分类号： H01L21/302 ,  H01L21/31

CPC分类号： H01L21/3105 ,  H01L21/321 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76859

摘要： Methods for fabricating interconnect structures are provided. An exemplary method for fabricating an interconnect comprises providing a substrate with a first dielectric layer thereon. At least one conductive feature is formed in the first dielectric layer. A conductive cap is selectively formed to overlie the conductive feature. A surface treatment is performed on the first dielectric layer and the conductive cap. A second dielectric layer is then formed to overlie the first dielectric layer.

摘要翻译： 提供制造互连结构的方法。 用于制造互连的示例性方法包括在其上提供其上具有第一介电层的衬底。 在第一介电层中形成至少一个导电特征。 选择性地形成导电盖以覆盖导电特征。 在第一电介质层和导电盖上进行表面处理。 然后形成第二电介质层以覆盖第一电介质层。

公开(公告)号：US07250683B2

公开(公告)日：2007-07-31

申请号：US11056758

申请日：2005-02-11

申请人： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L2221/1063

摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

摘要翻译： 公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。 通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。 在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。 所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

公开(公告)号：US20060189131A1

公开(公告)日：2006-08-24

申请号：US11067042

申请日：2005-02-24

申请人： Chung-Liang Chang ,  Shaulin Shue ,  Ming-Hsing Tsai

发明人： Chung-Liang Chang ,  Shaulin Shue ,  Ming-Hsing Tsai

IPC分类号： H01L21/44 ,  H01L21/302

CPC分类号： H01L21/3212 ,  H01L21/288 ,  H01L21/76849

摘要： A composition and process suitable for the passivation of metal lines, layers or surfaces, particularly for the passivation of copper in the fabrication of integrated circuit devices on wafer substrates. The process includes providing a novel composition solution in contact with a copper line, layer or surface on a substrate as the copper is subjected to chemical mechanical planarization (CMP). The composition includes reactive cations of a displacement metal which are suspended in solution and spontaneously displace the copper atoms in the copper in an oxidation/reduction reaction. The oxidized and displaced copper cations are carried away by the composition solution, and the newly-incorporated metal atoms in the copper substantially inhibit or prevent growth of copper oxides in the copper.

摘要翻译： 一种适用于金属线，层或表面的钝化的组合物和方法，特别是在晶片衬底上制造集成电路器件时铜的钝化。 该方法包括当铜经受化学机械平面化（CMP）时，提供与基底上的铜线，层或表面接触的新型组合物溶液。 组合物包括置换金属的反应性阳离子，其悬浮在溶液中并在氧化/还原反应中自发地置换铜中的铜原子。 氧化和置换的铜阳离子被组合物溶液带走，并且铜中新引入的金属原子基本上抑制或阻止铜中铜氧化物的生长。

公开(公告)号：US20050224359A1

公开(公告)日：2005-10-13

申请号：US10814175

申请日：2004-04-01

申请人： Hung-Wen Su ,  Chien-Hsueh Shih ,  Ming-Hsing Tsai

发明人： Hung-Wen Su ,  Chien-Hsueh Shih ,  Ming-Hsing Tsai

IPC分类号： C25D5/00 ,  C25D7/12 ,  C25D17/00 ,  C25D17/02 ,  H01L21/288

CPC分类号： H01L21/2885 ,  C25D7/123 ,  C25D17/001 ,  C25D17/02 ,  C25D21/02

摘要： Apparatus and method for metal electroplating. The apparatus for metal electroplating includes an electroplating tank for containing an electrolyte at a first temperature, a substrate holder for holding a semiconductor substrate, and a heater for heating the portion of the electrolyte adjacent to the substrate holder to a second temperature higher than the first temperature.

摘要翻译： 金属电镀设备及方法 用于金属电镀的设备包括用于在第一温度下容纳电解质的电镀槽，用于保持半导体衬底的衬底保持器和用于将邻近衬底保持器的部分电解质加热至高于第一温度的第二温度的加热器 温度。

公开(公告)号：US06649513B1

公开(公告)日：2003-11-18

申请号：US10146286

申请日：2002-05-15

申请人： Ming-Hsing Tsai ,  Shih-Wei Chou ,  Winston Shue ,  Mong-Song Liang

发明人： Ming-Hsing Tsai ,  Shih-Wei Chou ,  Winston Shue ,  Mong-Song Liang

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of fabricating a planarized metal structure comprising the following steps. A structure is provided. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having an opening formed therein and exposing at least a portion of the structure. A first-metal layer is formed over the patterned dielectric layer filling the opening. The first-metal layer including at least a doped metal portion adjacent the patterned dielectric layer. The doped metal portion being doped with a second-metal. The structure is annealed to form a second-metal oxide layer adjacent the patterned dielectric layer. The first-metal layer and the second-metal oxide layer are planarized using only a electropolishing process to remove the excess of the first-metal layer and the second-metal oxide layer from over the patterned dielectric layer and leaving a planarized metal structure within the opening.

摘要翻译： 一种制造平面化金属结构的方法，包括以下步骤。 提供了一种结构。 在该结构上形成图案化的介电层。 所述图案化介电层具有形成在其中的开口并暴露所述结构的至少一部分。 在填充开口的图案化电介质层上形成第一金属层。 第一金属层至少包括邻近图案化介电层的掺杂金属部分。 掺杂金属部分掺杂有第二金属。 将该结构退火以形成邻近图案化介电层的第二金属氧化物层。 第一金属层和第二金属氧化物层仅使用电解抛光工艺进行平面化，以从图案化的介电层上除去过量的第一金属层和第二金属氧化物层，并在其内部留下平坦化的金属结构 开放

公开(公告)号：US06573187B1

公开(公告)日：2003-06-03

申请号：US09378458

申请日：1999-08-20

申请人： Sheng-Hsiung Chen ,  Ming-Hsing Tsai

发明人： Sheng-Hsiung Chen ,  Ming-Hsing Tsai

IPC分类号： H01L21302

CPC分类号： H01L21/76835 ,  H01L21/76807

摘要： A new method is provided for creating a dual damascene structure. Two layers of dielectric are deposited in sequence. The lower layer of dielectric is the via dielectric and is selected such that it has a low etching rate (when compared with the upper layer of dielectric) and results in different volatile gas during the etch of the via. A first photoresist is patterned for the via, the etch for the via etches through both layers of dielectric. A second layer of photoresist is patterned for the trench etch, due to the difference in etch rate between the two layers of dielectric, the trench of the dual damascene structure is etched without further affecting the via etch in the lower layer of dielectric.

摘要翻译： 提供了一种创建双镶嵌结构的新方法。 依次沉积两层电介质。 电介质的下层是通孔电介质，并且被选择为使得其具有低蚀刻速率（当与电介质的上层相比时），并且在蚀刻通孔期间导致不同的挥发性气体。 对于通孔图案化第一光致抗蚀剂，蚀刻通过两个电介质层的通孔蚀刻。 为了沟槽蚀刻，第二层光致抗蚀剂被图案化，由于两层电介质之间的蚀刻速率差异，双镶嵌结构的沟槽被蚀刻，而不会进一步影响电介质的下层中的通孔蚀刻。

公开(公告)号：US06303498B1

公开(公告)日：2001-10-16

申请号：US09378497

申请日：1999-08-20

申请人： Sheng-Hsiung Chen ,  Ming-Hsing Tsai

发明人： Sheng-Hsiung Chen ,  Ming-Hsing Tsai

IPC分类号： H01L2144

CPC分类号： H01L21/76873 ,  H01L21/76843

摘要： A new method is provided whereby a copper seed layer is deposited over a barrier layer of TaN. Under the first embodiment of the invention, a doped seed layer is deposited over the barrier layer. Under the second embodiment of the invention a thin layer of metal is deposited over a seed layer of pure copper thereby preventing oxidation of the copper seed layer.

摘要翻译： 提供了一种新的方法，其中铜籽晶层沉积在TaN的阻挡层上。 在本发明的第一实施例中，在阻挡层上沉积掺杂种子层。 在本发明的第二实施例中，在纯铜的种子层上沉积薄层金属，从而防止铜籽晶层的氧化。

公开(公告)号：US06235637B1

公开(公告)日：2001-05-22

申请号：US09396518

申请日：1999-09-15

申请人： Sheng-Hsiung Chen ,  Ming-Hsing Tsai

发明人： Sheng-Hsiung Chen ,  Ming-Hsing Tsai

IPC分类号： H01L21311

CPC分类号： H01L23/544 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for marking a semiconductor wafer without inducing flat edge particles, using a laser scribing technique. The process begins by providing a semiconductor wafer having a marking area with a silicon top layer. The semiconductor wafer is coated with a photoresist layer. A volume of the photoresist layer and a volume of silicon top layer are removed corresponding to the intended marking. Optionally, the marking pattern can be further etched into the silicon top layer by anisotropic etching, using the photoresist layer as an etching mask. In another option, the laser scribing process can be set to scribe the marking pattern in the photoresist layer without scribing the silicon top layer. The marking pattern can then be anisotropically etched into the silicon top layer, using the photoresist layer as an etching mask. Alternatively, the photoresist layer can be patterned to form an opening in the photoresist layer over a marking area, thereby exposing the silicon top layer. The silicon top layer is then marked using a laser scribing technique, and the photoresist layer prevents contamination of the device areas of the wafer by the silicon particles generated by the laser scribing technique.

摘要翻译： 使用激光划线技术来标记半导体晶片而不引起平坦边缘颗粒的方法。 该过程开始于提供具有带硅顶层的标记区域的半导体晶片。 半导体晶片被涂覆有光致抗蚀剂层。 根据预期的标记去​​除光致抗蚀剂层的体积和硅顶层的体积。 可选地，使用光致抗蚀剂层作为蚀刻掩模，可以通过各向异性蚀刻将标记图案进一步蚀刻到硅顶层中。 在另一种选择中，可以设置激光划线工艺以划刻光致抗蚀剂层中的标记图案，而无需划线硅顶层。 然后可以使用光致抗蚀剂层作为蚀刻掩模将标记图案各向异性地蚀刻到硅顶层中。 或者，光致抗蚀剂层可以被图案化以在标记区域上在光致抗蚀剂层中形成开口，从而暴露硅顶层。 然后使用激光划线技术标记硅顶层，并且光致抗蚀剂层防止由激光划线技术产生的硅颗粒对晶片的器件区域的污染。

公开(公告)号：US08785321B2

公开(公告)日：2014-07-22

申请号：US13249823

申请日：2011-09-30

申请人： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

发明人： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.

摘要翻译： 提供了一种方法和系统，用于有效地改变半导体器件的金属互连的组成。 根据本公开的金属互连在电介质材料上具有中间层，中间层与主金属一起具有较高浓度的杂质金属，杂质金属具有比初级金属低的还原电位。 金属互连件在中间层的顶部具有金属合金互连的主层，被中间层包围，主层具有比中间层更高的一次金属浓度，其中，中间层和中间层的中间层和主要层 金属合金互连件均保持材料均匀性。

公开(公告)号：US07235482B2

公开(公告)日：2007-06-26

申请号：US10657505

申请日：2003-09-08

申请人： Chii-Ming Wu ,  Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/28562 ,  H01L23/53261 ,  H01L2924/0002 ,  H01L2924/00

摘要： An atomic layer deposition method is used to deposit a TiN or TiSiN film having a thickness of about 50 nm or less on a substrat. A titanium precursor which is tetrakis(dimethylamido)titanium (TDMAT), tetrakis(diethylamido)titanium (TDEAT), or Ti{OCH(CH3)2}4 avoids halide contamination from a titanium halide precursor and is safer to handle than a titanium nitrate. After a monolayer of the titanium precursor is deposited on a substrate, a nitrogen containing reactant is introduced to form a TiN monolayer which is followed by a second purge. For TiSiN, a silicon source gas is fed into the process chamber after the TiN monolayer formation. The process is repeated several times to produce a composite layer comprised of a plurality of monolayers that fills a contact hole. The ALD method is cost effective and affords an interconnect with lower impurity levels and better step coverage than conventional PECVD or CVD processes.

摘要翻译： 使用原子层沉积方法在基底上沉积厚度约为50nm或更小的TiN或TiSiN膜。 作为四（二甲基氨基）钛（TDMAT），四（二乙基氨基）钛（TDEAT）或Ti（OCH 2 CH 3）2） 4避免了来自卤化钛前体的卤化物污染，并且比硝酸钛更安全。 将钛前体的单层沉积在基底上之后，引入含氮反应物以形成TiN单层，随后进行第二次吹扫。 对于TiSiN，在TiN单层形成之后，将硅源气体进料到处理室中。 该过程重复几次以产生由填充接触孔的多个单层组成的复合层。 ALD方法具有成本效益，并且提供了比常规PECVD或CVD工艺更低的杂质水平和更好的阶梯覆盖的互连。