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    Method for differential selective deposition of metal for fabricating metal contacts in integrated semiconductor circuits
    41.
    发明授权
    Method for differential selective deposition of metal for fabricating metal contacts in integrated semiconductor circuits 失效
    用于在集成半导体电路中用于制造金属触点的金属的差分选择性沉积的方法

    公开(公告)号：US4617087A

    公开(公告)日：1986-10-14

    申请号：US780871

    申请日：1985-09-27

    申请人： Subramanian S. Iyer ,  Rajiv V. Joshi

    发明人： Subramanian S. Iyer ,  Rajiv V. Joshi

    IPC分类号： H01L21/3205 ,  C23C16/02 ,  C23C16/04 ,  C23C16/06 ,  C23F4/00 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  C23F1/02 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

    CPC分类号： H01L21/76879 ,  C23C16/0281 ,  C23C16/04 ,  C23C16/06 ,  C23F4/00 ,  H01L21/28562

    摘要： A deposition technique for forming metal regions on semiconductor substrates, and more particularly to a fabrication method for the differential selective deposition of tungsten for forming tungsten contacts on an integrated circuit chip.Tungsten hexafluoride gas (WF6) is introduced into a deposition chamber containing a silicon substrate with an apertured silicon dioxide mask layer thereon. The exposed Si surfaces on which the selective deposition is to be performed, are first converted to W surfaces by the substitution reaction:2WF6+3Si=2W+3SiF4After the surface has been substituted, the WF.sub.6 is mixed with H.sub.2 as to give deposition of W by partially preferential nucleation on the already converted W surfaces. Then NF.sub.3 is bled into the system and a plasma is struck in the reaction chamber to create a simultaneous etching condition for the tungsten.The amount of NF3 and the plasma power coupled into the chamber are such as to ensure that the SiO.sub.2 surface is kept clean at all times. Thus any nuclei that may be formed on the SiO.sub.2 surface, are immediately cleaned out. Since the deposition rate on the exposed W surfaces is much higher than on the SiO.sub.2 surfaces, there will be net deposition on these areas in spite of the etching action, albeit at a lower rate.

    摘要翻译： 一种用于在半导体衬底上形成金属区域的沉积技术，更具体地说，涉及用于在集成电路芯片上形成钨触点的钨的差分选择性沉积的制造方法。 将六氟化钨气体（WF6）引入到其中具有带孔二氧化硅掩模层的硅衬底的沉积室中。 要进行选择性沉积的暴露的Si表面首先通过取代反应转化为W表面：2WF6 + 3Si = 2W + 3SiF4在表面被取代后，将WF6与H 2混合，使沉积 W在已经转化的W表面上部分优先成核。 然后将NF3放入系统中，并在反应室中撞击等离子体，以产生钨的同时蚀刻条件。 NF3的量和耦合到腔室中的等离子体功率是确保SiO 2表面始终保持清洁。 因此，可以立即清除可能形成在SiO2表面上的任何核。 由于暴露的W表面上的沉积速率远高于SiO 2表面上的沉积速率，尽管蚀刻作用仍然存在这些区域上的净沉积，尽管速率较低。

    STRUCTURE AND METHOD TO FORM EDRAM ON SOI SUBSTRATE
    42.
    发明申请
    STRUCTURE AND METHOD TO FORM EDRAM ON SOI SUBSTRATE 有权
    在SOI衬底上形成EDRAM的结构和方法

    公开(公告)号：US20120171827A1

    公开(公告)日：2012-07-05

    申请号：US13417900

    申请日：2012-03-12

    申请人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

    发明人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/945

    摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

    摘要翻译： 提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和 内电极 以及位于沟槽电容器上方的半导体器件。 半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。 存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

    Communicating system information in a wireless communication network
    43.
    发明授权
    Communicating system information in a wireless communication network 有权
    在无线通信网络中通信系统信息

    公开(公告)号：US08189522B2

    公开(公告)日：2012-05-29

    申请号：US12392188

    申请日：2009-02-25

    申请人： Subramanian S. Iyer ,  Christopher R. Cushing ,  Ajaykumar R. Idnani ,  David R. Maas ,  J. Chris Stanaway

    发明人： Subramanian S. Iyer ,  Christopher R. Cushing ,  Ajaykumar R. Idnani ,  David R. Maas ,  J. Chris Stanaway

    IPC分类号： H04W4/00 ,  H04L12/26 ,  H04L12/54

    CPC分类号： H04W48/12 ,  H04W84/18

    摘要： An apparatus and method for communicating system information in a wireless communication network. A first step 200 includes defining unicast threshold parameter(s). A next step 201 includes receiving a request for system information. A next step 202, 204 includes determining if the system information exceeds the threshold parameter(s). A next step 206-216 includes scheduling an ad-hoc broadcast of the system information if the system information exceeds the threshold parameter(s). A next step 218 includes sending a pointer to the scheduled ad-hoc broadcast. A next step 220 includes broadcasting the network service provider information per the schedule.

    摘要翻译： 一种用于在无线通信网络中传送系统信息的装置和方法。 第一步骤200包括定义单播阈值参数。 下一步骤201包括接收对系统信息的请求。 下一步骤202,204包括确定系统信息是否超过阈值参数。 如果系统信息超过阈值参数，则下一步骤206-216包括调度系统信息的自组播广播。 下一步骤218包括发送指向预定的自组播广播的指针。 下一步骤220包括根据时间表广播网络服务提供商信息。

    CELLULAR COMMUNICATION SYSTEM AND METHOD OF OPERATION THEREFOR
    45.
    发明申请
    CELLULAR COMMUNICATION SYSTEM AND METHOD OF OPERATION THEREFOR 有权
    蜂窝通信系统及其操作方法

    公开(公告)号：US20100120437A1

    公开(公告)日：2010-05-13

    申请号：US12530785

    申请日：2008-04-10

    申请人： Gerard T. Foster ,  Trevor T. Hanna ,  Subramanian S. Iyer ,  Luis Lopes ,  Howard J. Thomas

    发明人： Gerard T. Foster ,  Trevor T. Hanna ,  Subramanian S. Iyer ,  Luis Lopes ,  Howard J. Thomas

    IPC分类号： H04W36/00

    CPC分类号： H04W36/04 ,  H04W36/32

    摘要： A cellular communication system comprises an access point (101) which supports an underlay cell of a first cell on an underlay frequency using another frequency. A proximity detector (113) detects user equipment (109) in response to a wireless transmission therefrom, which uses a different transmission technology from a transmission of the cellular communication system. In response to the proximity detection, the access point (101) temporarily transmits a pilot signal on the first cell frequency. The user equipment (109) is then switched to the access point (109) and the underlay frequency in response to a detection indication from the user equipment (109) indicating that the pilot signal has been detected. Following the switch the access point (101) terminates the transmission of the pilot signal.

    摘要翻译： 蜂窝通信系统包括接入点（101），其使用另一频率来支持底层频率上的第一小区的底层小区。 接近检测器（113）响应于来自其的无线传输来检测用户设备（109），其使用与蜂窝通信系统的传输不同的传输技术。 响应于接近检测，接入点（101）在第一小区频率上临时发送导频信号。 响应于来自用户设备（109）的指示已经检测到导频信号的检测指示，用户设备（109）然后切换到接入点（109）和底层频率。 在切换之后，接入点（101）终止导频信号的发送。

    ELECTRICAL FUSE STRUCTURE FOR HIGHER POST-PROGRAMMING RESISTANCE
    46.
    发明申请
    ELECTRICAL FUSE STRUCTURE FOR HIGHER POST-PROGRAMMING RESISTANCE 失效
    用于更高后编程电阻的电熔丝结构

    公开(公告)号：US20080217733A1

    公开(公告)日：2008-09-11

    申请号：US11683071

    申请日：2007-03-07

    申请人： Subramanian S. Iyer ,  Deok-Kee Kim ,  Chandrasekara Kothandaraman ,  Byeongju Park

    发明人： Subramanian S. Iyer ,  Deok-Kee Kim ,  Chandrasekara Kothandaraman ,  Byeongju Park

    IPC分类号： H01L23/58

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides an electrical fuse structure for achieving a post-programming resistance distribution with higher resistance values and to enhance the reliability of electrical fuse programming. A partly doped electrical fuse structure with undoped semiconductor material in the cathode combined with P-doped semiconductor material in the fuselink and anode is disclosed and the data supporting the superior performance of the disclosed electrical fuse is shown.

    摘要翻译： 本发明提供一种用于实现具有更高电阻值的后编程电阻分布并提高电熔丝编程的可靠性的电熔丝结构。 公开了在阴极中与掺杂了P掺杂的半导体材料结合在阴极中的未掺杂半导体材料的部分掺杂的电熔丝结构，并且示出了所公开的电熔丝的优异性能的数据。

    Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same
    48.
    发明授权
    Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same 有权
    与中间线金属触点集成的沟槽金属 - 绝缘体金属（MIM）电容器及其制造方法

    公开(公告)号：US07276751B2

    公开(公告)日：2007-10-02

    申请号：US11162413

    申请日：2005-09-09

    申请人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

    发明人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

    IPC分类号： H01L29/76

    CPC分类号： H01L27/10861 ,  H01L28/91 ,  H01L29/945

    摘要： The present invention relates to a semiconductor device that contains at least one trench metal-oxide-metal (MIM) capacitor and at least one other logic circuitry component, preferably at least one field effect transistor (FET). The trench MIM capacitor is located in a trench in a substrate and comprises inner and outer metallic electrode layers with a dielectric layer therebetween. The FET comprises a source region, a drain region, a channel region, and at least one metal contact connected with the source or drain region. The present invention also relates to a fabrication process, which integrates the processing steps for fabricating the trench MIM capacitor with the conventional middle-of-line processing steps for fabricating metal contacts, so that the inner metallic electrode layer of the trench MIM capacitor and the metal contact of the FET or other logic circuitry components are formed by a single middle-of-line processing step and comprise essentially the same metallic material.

    摘要翻译： 本发明涉及一种半导体器件，其包含至少一个沟槽金属氧化物金属（MIM）电容器和至少一个其它逻辑电路部件，优选至少一个场效应晶体管（FET）。 沟槽MIM电容器位于衬底中的沟槽中，并且包括其间具有介电层的内部和外部金属电极层。 FET包括源极区，漏极区，沟道区以及与源极或漏极区连接的至少一个金属接触。 本发明还涉及一种制造工艺，其将用于制造沟槽MIM电容器的处理步骤与用于制造金属触点的常规中间线处理步骤相结合，使得沟槽MIM电容器的内部金属电极层和 FET或其他逻辑电路部件的金属接触通过单个中间线处理步骤形成并且包括基本上相同的金属材料。

    Gain cell structure with deep trench capacitor
    50.
    发明授权
    Gain cell structure with deep trench capacitor 有权
    具有深沟槽电容器的增益单元结构

    公开(公告)号：US06747890B1

    公开(公告)日：2004-06-08

    申请号：US10249347

    申请日：2003-04-02

    申请人： Toshiaki Kirihata ,  Subramanian S. Iyer ,  John W. Golz

    发明人： Toshiaki Kirihata ,  Subramanian S. Iyer ,  John W. Golz

    IPC分类号： G11C1124

    CPC分类号： H01L27/10844 ,  G11C2207/104 ,  H01L27/108 ,  H01L27/11

    摘要： Gain cells adapted to trench capacitor technology and memory array configured with these gain cells are described. The 3T and 2T gain cells of the present invention include a trench capacitor attached to a storage node such that the storage voltage is maintained for a long retention time. The gate of the gain transistor and the trench capacitor are placed alongside the read and write wordline. This arrangement makes it possible to have the gain transistor directly coupled to the trench capacitor, resulting in a smaller cell size. The memory cell includes a first transistor provided with a gate, a source, and a drain respectively coupled to a read wordline, a first node, and a read bitline; a second transistor having a gate, a source, and a drain respectively coupled to a storage node, to a voltage source, and to the first node; a third transistor having a gate, a source, and a drain respectively coupled to a write wordline, the storage node, and a write bitline; and a capacitor having a first terminal connected to the storage node and a second terminal connected to a voltage source.

    摘要翻译： 描述适用于沟槽电容器技术的增益单元和配置有这些增益单元的存储器阵列。 本发明的3T和2T增益单元包括连接到存储节点的沟槽电容器，使得存储电压保持长的保留时间。 增益晶体管的栅极和沟槽电容器放置在读写字线旁边。 这种布置使得可以使增益晶体管直接耦合到沟槽电容器，导致更小的单元尺寸。 存储单元包括：第一晶体管，其设置有分别耦合到读字线，第一节点和读位线的栅极，源极和漏极; 第二晶体管，其具有分别耦合到存储节点的栅极，源极和漏极，电压源以及所述第一节点; 第三晶体管，具有分别耦合到写入字线，存储节点和写入位线的栅极，源极和漏极; 以及电容器，其具有连接到存储节点的第一端子和连接到电压源的第二端子。