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    Vacuum-cavity MEMS resonator
    45.
    发明授权
    Vacuum-cavity MEMS resonator 失效
    真空腔MEMS谐振器

    公开(公告)号：US06808954B2

    公开(公告)日：2004-10-26

    申请号：US09949368

    申请日：2001-09-07

    Applicant: Qing Ma ,  Peng Cheng ,  Valluri Rao

    Inventor： Qing Ma ,  Peng Cheng ,  Valluri Rao

    IPC: H01L2100

    CPC classification number: B81B7/0077 ,  H03H3/0072 ,  H03H9/1057 ,  H03H9/2405 ,  H03H9/2431 ,  H03H9/2457 ,  H03H9/2463 ,  H03H2009/02503 ,  H03H2009/02511

    Abstract: A microelectromechanical (MEMS) resonator with a vacuum-cavity is fabricated using polysilicon-enabled release methods. A vacuum-cavity surrounding the MEMS beam is formed by removing release material that surrounds the beam and sealing the resulting cavity under vacuum by depositing a layer of nitride over the structure. The vacuum-cavity MEMS resonators have cantilever beams, bridge beams or breathing-bar beams.

    Abstract translation: 具有真空腔的微机电（MEMS）谐振器是使用多晶硅启用释放方法制造的。 围绕MEMS光束的真空腔通过去除围绕光束的释放材料并通过在结构上沉积氮化层而在真空下密封所得空腔来形成。 真空腔MEMS谐振器具有悬臂梁，桥梁或呼吸杆梁。

    Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition
    47.
    发明授权
    Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition 失效

    公开(公告)号：US6063688A

    公开(公告)日：2000-05-16

    申请号：US939578

    申请日：1997-09-29

    Applicant: Brian S. Doyle ,  Peng Cheng

    Inventor： Brian S. Doyle ,  Peng Cheng

    IPC: H01L21/033 ,  H01L21/335 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/76

    CPC classification number: B82Y10/00 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/762 ,  H01L21/823437 ,  H01L29/66439 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/946 ,  Y10S438/947

    Abstract: The invention relates to a method of forming reduced feature size spacers. The method includes providing a semiconductor substrate having an area region; patterning a first spacer over a portion of the area region of the substrate, the first spacer having a first thickness and opposing side portions; patterning a pair of second spacers, each second spacer adjacent to a side portion of the first spacer, each second spacer having a second thickness in opposing side portions, wherein the second thickness is less than the first thickness; removing the first spacer; patterning a plurality of third spacers, each third spacer adjacent to one of the side portions of one of the second spacers, each one of the third spacers having a third thickness, wherein the third thickness is less than the second thickness; and removing the second spacers. The invention also relates to a field of effect transistor. The transistor includes a semiconductor substrate having a source region and a drain region; a gate area of the substrate surface; a channel region in the substrate having a cross-sectional area defined by a portion of the gate area, a channel length measured accross a portion of the channel region between the source region and the drain region; and a trench formed in a portion of the channel region, the trench having a trench length substantially equivalent to the channel length.

    Method of fabricating next-to-minimum-size transistor gate using mask-edge gate definition technique
    48.
    发明授权
    Method of fabricating next-to-minimum-size transistor gate using mask-edge gate definition technique 失效
    使用掩模边缘栅极定义技术制造下一个最小尺寸晶体管栅极的方法

    公开(公告)号：US6022815A

    公开(公告)日：2000-02-08

    申请号：US775412

    申请日：1996-12-31

    Applicant: Brian S. Doyle ,  Chunlin Liang ,  Peng Cheng ,  Qi-De Qian

    Inventor： Brian S. Doyle ,  Chunlin Liang ,  Peng Cheng ,  Qi-De Qian

    IPC: H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/3205

    CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/823456

    Abstract: A method of fabricating minimum size and next-to-minimum size electrically conductive members using a litho-less process is disclosed. A substrate is provided, and a layer of gate dielectric material is formed on the substrate. A layer of electrically conductive material is formed over the gate dielectric material. A first mask is used to form a hard mask. A layer of first spacer material is deposited over the existing structures, and the layer of first spacer material is etched back to form spacers adjacent to the hard mask. The width of the first spacers determines the minimum size gate length. A layer of second spacer material is deposited over the existing structures, including the hard mask and first spacers. The layer of second spacer material is etched back to form a second set of spacers adjacent to the first spacers. The width of the first and second spacers together determine the next-to-minimum size gate length. A second mask is used to protect the portion of the second spacers which are to be used to define next-to-minimum size gates, and the unprotected second spacers and the hard mask are removed. The exposed electrically conductive material is removed. The remaining spacers are then removed, leaving minimum size and next-to-minimum size gates.

    Abstract translation: 公开了使用无平滑工艺制造最小尺寸和接下来尺寸的导电构件的方法。 提供衬底，并且在衬底上形成栅极电介质材料层。 在栅极电介质材料上方形成一层导电材料。 使用第一个掩模形成硬掩模。 在现有结构上沉积第一间隔物层，并且将第一间隔物材料层回蚀刻以形成与硬掩模相邻的间隔物。 第一间隔物的宽度决定了栅极长度的最小尺寸。 在现有结构上沉积第二间隔物层，包括硬掩模和第一间隔物。 第二间隔物材料层被回蚀刻以形成邻近第一间隔物的第二组间隔物。 第一和第二间隔物的宽度一起确定下一个至最小尺寸的栅极长度。 使用第二掩模来保护用于限定下一个至最小尺寸的门的第二间隔物的部分，并且去除未受保护的第二间隔物和硬掩模。 暴露的导电材料被去除。 然后移除剩余的间隔物，留下最小尺寸和下至最小尺寸的门。

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