公开(公告)号：US07006379B2

公开(公告)日：2006-02-28

申请号：US11068228

申请日：2005-03-01

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0483 ,  H01L27/115

摘要： A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.

摘要翻译： 一种包括存储单元单元的半导体存储器，所述存储单元单元包括：多个存储单元，其中当前端子之间的每个电导根据保持的数据而改变，每个存储单元具有串联连接在第一端子和第二端子之间的多个电流端子 终端，并且每个都能够电气地重写数据; 将所述第一端子电连接到数据传输线路的第一选择开关元件; 以及用作将所述第二端子连接到参考电位线的第二选择开关元件的MISFET，其中所述半导体存储器具有用于将所述存储单元单元的第一和第二选择开关元件强制为导通的数据读取模式，施加读取电压 用于根据所选择的存储单元的数据将当前端子之间的路径强制为导通或截止，到所选存储单元的控制电极，施加通过电压，以迫使当前端子之间的路径导通，而不管 除了所述选择的存储单元之外的每个存储单元的数据，还包括除了所选择的存储单元之外的每个存储单元的控制电极，以及检测所述数据传输线与所述参考电压之间的电流的存在和否定 电位线，并且在所述数据读取模式中，将所述MISFET的电流端子之间的电导设置为低于电导， 关于当前终端之间的电导被设置为最低的情况，关于除了所选择的存储单元之外的至少一个存储单元。

公开(公告)号：US06958938B2

公开(公告)日：2005-10-25

申请号：US11007461

申请日：2004-12-09

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Yuji Takeuchi

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Yuji Takeuchi

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/3445 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3468

摘要： A data writing method for a semiconductor memory device includes writing data into the first memory cell, rewriting the data into the first memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one first reference threshold voltage, writing data into the second memory cell following writing the data into the first memory cell, and rewriting the data into the first memory cell following writing the data into the second memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one second reference threshold voltage. The first reference threshold voltage is set to be different from the second reference threshold voltage.

摘要翻译： 半导体存储器件的数据写入方法包括将数据写入第一存储单元，当确定第一存储单元的数据不足时，将数据重新写入第一存储器单元作为验证第一存储器的数据的结果 在一个第一参考阈值电压下，将数据写入第一存储单元之后，将数据写入第二存储单元，并且当数据不足时将数据写入第二存储单元中 作为第一存储单元的数据在一秒钟的参考阈值电压下进行验证的结果来确定第一存储单元。 第一参考阈值电压被设置为不同于第二参考阈值电压。

公开(公告)号：US06925009B2

公开(公告)日：2005-08-02

申请号：US10920355

申请日：2004-08-18

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/26 ,  G11C16/0483 ,  H01L27/115

摘要： A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.

摘要翻译： 一种包括存储单元单元的半导体存储器，所述存储单元单元包括：多个存储单元，其中当前端子之间的每个电导根据保持的数据而改变，每个存储单元具有串联连接在第一端子和第二端子之间的多个电流端子 终端，并且每个都能够电气地重写数据; 将所述第一端子电连接到数据传输线路的第一选择开关元件; 以及用作将所述第二端子连接到参考电位线的第二选择开关元件的MISFET，其中所述半导体存储器具有用于将所述存储单元单元的第一和第二选择开关元件强制为导通的数据读取模式，施加读取电压 用于根据所选择的存储单元的数据将当前端子之间的路径强制为导通或截止，到所选存储单元的控制电极，施加通过电压，以迫使当前端子之间的路径导通，而不管 除了所述选择的存储单元之外的每个存储单元的数据，还包括除了所选择的存储单元之外的每个存储单元的控制电极，以及检测所述数据传输线与所述参考电压之间的电流的存在和否定 电位线，并且在所述数据读取模式中，将所述MISFET的电流端子之间的电导设置为低于电导， 关于当前终端之间的电导被设置为最低的情况，关于除了所选择的存储单元之外的至少一个存储单元。

公开(公告)号：US20050157578A1

公开(公告)日：2005-07-21

申请号：US11074801

申请日：2005-03-09

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Hiroyuki Nitta

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Hiroyuki Nitta

IPC分类号： G11C16/02 ,  G06F11/10 ,  G11C8/00 ,  G11C11/34 ,  G11C16/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  G11C29/00 ,  G11C29/04 ,  G11C29/42 ,  G11C29/52 ,  H01L21/8247 ,  H01L27/00 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G06F11/1008 ,  G06F11/108 ,  G11C7/22 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3454 ,  G11C29/50004 ,  G11C29/52 ,  G11C29/76 ,  G11C29/82 ,  G11C29/84 ,  G11C2029/0409 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.

公开(公告)号：US20050093047A1

公开(公告)日：2005-05-05

申请号：US10954238

申请日：2004-10-01

申请人： Akira Goda ,  Mitsuhiro Noguchi

发明人： Akira Goda ,  Mitsuhiro Noguchi

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/00 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573

摘要： A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve the yield, and trench grooves are formed to be deep in the high voltage transistor region of the peripheral circuit region, in particular in a high voltage transistor region thereof, in order to improve the element isolation withstand voltage. A plurality of memory cell transistors having an ONO layer 15 serving as a charge accumulating insulating layer are provided in the memory cell region, where element isolation grooves 6 for these memory cell transistors are narrow and shallow. Two types of transistors, one for high voltage and the other for low voltage, having gate insulating layers 16 or 17, which are different from the ONO layer 15 in the memory cell region, are provided in the peripheral circuit region, where at least element isolation grooves 23 for high voltage transistors are wide and deep. In this way, it is possible to improve the degree of integration and yield in the memory cell region, and secure withstand voltage in the peripheral circuit region.

摘要翻译： 提出了具有存储单元区域和外围电路区域的半导体存储器件以及制造这种半导体存储器件的方法，其中沟槽形成在存储单元区域中较浅以提高产量， 并且在周边电路区域的高电压晶体管区域，特别是在其高压晶体管区域中形成深沟槽，以便提高元件隔离耐受电压。 在存储单元区域中设置有多个具有作为电荷累积绝缘层的ONO层15的存储单元晶体管，其中用于这些存储单元晶体管的元件隔离槽6窄而浅。 在外围电路区域中设置两个类型的晶体管，一个用于高电压，另一个用于低电压，具有与存储单元区域中的ONO层15不同的栅极绝缘层16或17，其中至少元件 用于高压晶体管的隔离槽23宽而深。 以这种方式，可以提高存储单元区域的集成度和产量，并且确保外围电路区域中的耐受电压。

公开(公告)号：US20050045941A1

公开(公告)日：2005-03-03

申请号：US10893295

申请日：2004-07-19

申请人： Koichi Kurita ,  Mitsuhiro Noguchi ,  Akira Goda

发明人： Koichi Kurita ,  Mitsuhiro Noguchi ,  Akira Goda

IPC分类号： G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324

摘要： According to the present invention, there is provided a nonvolatile semiconductor memory capable of electrically writing and erasing information, comprising: a semiconductor substrate; source and drain regions formed at a predetermined spacing in a surface portion of said semiconductor substrate; a channel region positioned between said source and drain regions; a floating gate electrode formed on said cannel region via a first insulating film; a control gate electrode including a semiconductor layer formed on said floating gate electrode via a second insulating film, and a metal layer formed on said semiconductor layer; and an oxidation-resistant third insulating film formed on said control gate electrode, wherein the nonvolatile semiconductor memory further comprises an oxidation-resistant fourth insulating film so formed as to cover at least sidewalls of said metal layer, and said fourth insulating film is formed from the sidewalls of said metal layer to at least portions of sidewalls of said semiconductor layer of said control gate electrode.

摘要翻译： 根据本发明，提供一种能够电写入和擦除信息的非易失性半导体存储器，包括：半导体衬底; 在所述半导体衬底的表面部分中以预定间隔形成的源区和漏区; 位于所述源区和漏区之间的沟道区; 经由第一绝缘膜形成在所述槽区上的浮栅电极; 包括经由第二绝缘膜形成在所述浮置栅电极上的半导体层的控制栅电极和形成在所述半导体层上的金属层; 以及形成在所述控制栅电极上的抗氧化的第三绝缘膜，其中所述非易失性半导体存储器还包括形成为至少覆盖所述金属层的侧壁的耐氧化的第四绝缘膜，并且所述第四绝缘膜由 所述金属层的侧壁至所述控制栅电极的所述半导体层的侧壁的至少部分。

公开(公告)号：US20050018485A1

公开(公告)日：2005-01-27

申请号：US10920355

申请日：2004-08-18

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C16/26 ,  G11C16/0483 ,  H01L27/115

摘要： A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.

摘要翻译： 一种包括存储单元单元的半导体存储器，所述存储单元单元包括：多个存储单元，其中当前端子之间的每个电导根据保持的数据而改变，每个存储单元具有串联连接在第一端子和第二端子之间的多个电流端子 终端，并且每个都能够电气地重写数据; 将所述第一端子电连接到数据传输线路的第一选择开关元件; 以及用作将所述第二端子连接到参考电位线的第二选择开关元件的MISFET，其中所述半导体存储器具有用于将所述存储单元单元的第一和第二选择开关元件强制为导通的数据读取模式，施加读取电压 用于根据所选择的存储单元的数据将当前端子之间的路径强制为导通或截止，到所选存储单元的控制电极，施加通过电压，以迫使当前端子之间的路径导通，而不管 除了所述选择的存储单元之外的每个存储单元的数据，还包括除了所选择的存储单元之外的每个存储单元的控制电极，以及检测所述数据传输线与所述参考电压之间的电流的存在和否定 电位线，并且在所述数据读取模式中，将所述MISFET的电流端子之间的电导设置为低于电导， 关于当前终端之间的电导被设置为最低的情况，关于除了所选择的存储单元之外的至少一个存储单元。

公开(公告)号：US06828624B1

公开(公告)日：2004-12-07

申请号：US09556777

申请日：2000-04-25

申请人： Akira Goda ,  Riichiro Shirota ,  Kazuhiro Shimizu ,  Hiroaki Hazama ,  Hirohisa Iizuka ,  Seiichi Aritome ,  Wakako Moriyama

发明人： Akira Goda ,  Riichiro Shirota ,  Kazuhiro Shimizu ,  Hiroaki Hazama ,  Hirohisa Iizuka ,  Seiichi Aritome ,  Wakako Moriyama

IPC分类号： H01L29792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11543 ,  Y10S257/909

摘要： A nonvolatile semiconductor memory device includes comprises: an element isolation region being in contact with a first element region, an insulating film covering a memory cell, a peripheral transistor and the element isolation region, an inter-level insulating film provided on the surface of the insulating film, and a contact hole provided in the inter-level insulating film and the insulating film. The inter-level insulating film contains an insulator different from the insulating film. The contact hole reaches at least one of source and drain diffusion layers of the memory cell and overlaps the element isolation region. The insulating film contains an insulator different from the element isolation region and the insulating film is harder for an oxidizing agent to pass therethrough than a silicon oxide film. A surface of the insulating film is oxidized.

摘要翻译： 非易失性半导体存储器件包括：与第一元件区域接触的元件隔离区域，覆盖存储单元的绝缘膜，外围晶体管和元件隔离区域，设置在第一元件区域的表面上的层间绝缘膜 绝缘膜和设置在层间绝缘膜和绝缘膜中的接触孔。 层间绝缘膜含有与绝缘膜不同的绝缘体。 接触孔到达存储单元的源极和漏极扩散层中的至少一个并且与元件隔离区域重叠。 绝缘膜含有与元件隔离区不同的绝缘体，绝缘膜比氧化硅膜更难以通过氧化剂。 绝缘膜的表面被氧化。

公开(公告)号：US08982631B2

公开(公告)日：2015-03-17

申请号：US12702948

申请日：2010-02-09

申请人： Yijie Zhao ,  Akira Goda

发明人： Yijie Zhao ,  Akira Goda

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/12 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3454

摘要： Memory devices and programming methods for memories are disclosed, such as those adapted to program a memory using an increasing channel voltage for a first portion of programming, and an increasing but reduced channel voltage for a second portion of programming.

摘要翻译： 公开了用于存储器的存储器件和编程方法，诸如适于使用用于编程的第一部分的增加的沟道电压对存储器进行编程的那些，以及用于第二部分编程的增加但是减小的沟道电压。

公开(公告)号：US20140036590A1

公开(公告)日：2014-02-06

申请号：US13564458

申请日：2012-08-01

申请人： Peter Sean Feeley ,  Koji Sakui ,  Akira Goda

发明人： Peter Sean Feeley ,  Koji Sakui ,  Akira Goda

IPC分类号： G11C16/04

摘要： Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.

摘要翻译： 公开了诸如包括包含电荷存储装置串的存储器单元块的方法和装置。 每个串可以包括以多层形成的多个电荷存储装置。 该装置可以包括由串共享的多个接入线。 多个接入线路中的每一个可以耦合到与多个层级的相应层对应的电荷存储装置。 该装置可以包括与弦相关联的多个子源。 多个子源中的每一个可以耦合到字符串的多个子集的相应子集的每个串的源选择门，并且每个子源可以独立地从其他子源中选择以选择字符串 独立于对应于其他子集的其他字符串。