公开(公告)号：US08797792B2

公开(公告)日：2014-08-05

申请号：US14022364

申请日：2013-09-10

Applicant: QUALCOMM Incorporated

Inventor： Hari M. Rao ,  Jung Pil Kim ,  Seung H. Kang ,  Xiaochun Zhu ,  Tae Hyun Kim ,  Kangho Lee ,  Xia Li ,  Wah Nam Hsu ,  Wuyang Hao ,  Jungwon Suh ,  Nicholas K. Yu ,  Matthew Michael Nowak ,  Steven M. Millendorf ,  Asaf Ashkenazi

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/14 ,  G11C17/02 ,  G11C17/16 ,  G11C29/02

CPC classification number: G11C11/16 ,  G11C11/14 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  G11C17/16 ,  G11C29/027

Abstract: A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ.

Abstract translation: 存储器件包括磁性隧道结（MTJ）位单元。 MTJ位单元包括第一MTJ和第二MTJ。 存储器件还包括编程电路，其被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个来在位单元处产生不可逆状态。 不可逆状态对应于通过比较在第一MTJ读取的第一值和在第二MTJ读取的第二值确定的MTJ比特单元的值。

公开(公告)号：US20140210043A1

公开(公告)日：2014-07-31

申请号：US14227415

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  John Jianhong Zhu ,  Xia Li

IPC: H01L23/525 ,  H01L21/768

CPC classification number: H01L23/5252 ,  G11C17/16 ,  H01L23/5228 ,  H01L27/11206 ,  H01L27/11286 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One feature pertains to an integrated circuit that includes an antifuse having a conductor-insulator-conductor structure. The antifuse includes a first conductor plate, a dielectric layer, and a second conductor plate, where the dielectric layer is interposed between the first and second conductor plates. The antifuse transitions from an open circuit state to a closed circuit state if a programming voltage VPP greater than or equal to a dielectric breakdown voltage VBD of the antifuse is applied to the first conductor plate and the second conductor plate. The first conductor plate has a total edge length that is greater than two times the sum of its maximum width and maximum length dimensions. The first conductor plate's top surface area may also be less than the product of its maximum length and maximum width.

Abstract translation: 一个特征涉及包括具有导体 - 绝缘体 - 导体结构的反熔丝的集成电路。 反熔丝包括第一导体板，电介质层和第二导体板，其中电介质层插在第一和第二导体板之间。 如果大于等于反熔丝的绝缘击穿电压VBD的编程电压VPP被施加到第一导体板和第二导体板，则反熔丝从开路状态转变到闭合状态。 第一导体板的总边缘长度大于其最大宽度和最大长度尺寸之和的两倍。 第一导体板的顶表面积也可以小于其最大长度和最大宽度的乘积。

公开(公告)号：US20140203381A1

公开(公告)日：2014-07-24

申请号：US13748979

申请日：2013-01-24

Applicant: QUALCOMM INCORPORATED

Inventor： Xiaochun Zhu ,  Xia Li ,  Wei-Chuan Chen ,  Seung H. Kang

IPC: H01L43/12 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: Material surrounding a magnetic tunnel junction (MTJ) device region of a multi-layer starting structure is etched, forming an MTJ device pillar having an MTJ layer with a chemically damaged peripheral edge region. De-nitridation or de-oxidation, or both, restore the chemically damaged peripheral region to form an edge-restored MTJ layer. An MTJ edge restoration assist layer is formed on the edge-restored MTJ layer. An MTJ-edge-protect layer is formed on the insulating MTJ-edge-restoration-assist layer.

Abstract translation: 蚀刻围绕多层起始结构的磁性隧道结（MTJ）器件区域的材料，形成具有化学损伤的外围边缘区域的MTJ层的MTJ器件柱。 脱氮或脱氧，或两者恢复化学损伤的外围区域，形成边缘恢复的MTJ层。 在边缘恢复的MTJ层上形成MTJ边缘恢复辅助层。 在绝缘MTJ边缘恢复辅助层上形成MTJ边缘保护层。

公开(公告)号：US20140010006A1

公开(公告)日：2014-01-09

申请号：US14022364

申请日：2013-09-10

Applicant: QUALCOMM Incorporated

Inventor： Hari M. Rao ,  Jung Pill Kim ,  Seung H. Kang ,  Xiaochun Zhu ,  Taehyun Kim ,  Kangho Lee ,  Xia Li ,  Wah Nam Hsu ,  Wuyang Hao ,  Jungwon Suh ,  Nicholas K. Yu ,  Matthew M. Nowak ,  Steven M. Millendorf ,  Asaf Ashkenazi

IPC: G11C11/14

CPC classification number: G11C11/16 ,  G11C11/14 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  G11C17/16 ,  G11C29/027

Abstract: A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ.

Abstract translation: 存储器件包括磁性隧道结（MTJ）位单元。 MTJ位单元包括第一MTJ和第二MTJ。 存储器件还包括编程电路，其被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个来在位单元处产生不可逆状态。 不可逆状态对应于通过比较在第一MTJ读取的第一值和在第二MTJ读取的第二值确定的MTJ比特单元的值。

公开(公告)号：US20130288395A1

公开(公告)日：2013-10-31

申请号：US13925953

申请日：2013-06-25

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung H. Kang

IPC: H01L43/12 ,  G06F17/50

CPC classification number: G06F17/50 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming an MTJ cap layer on an MTJ structure and forming a top electrode layer coupled to the MTJ cap layer. The top electrode layer includes at least two layers and one layer of the two layers includes a nitrified metal.

Abstract translation: 在特定实施例中，形成磁性隧道结（MTJ）器件的方法包括在MTJ结构上形成MTJ覆盖层并形成耦合到MTJ覆盖层的顶部电极层。 顶部电极层包括至少两层，两层的一层包括硝化金属。

公开(公告)号：US12051534B2

公开(公告)日：2024-07-30

申请号：US17226744

申请日：2021-04-09

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Haining Yang

IPC: H01F27/29 ,  H01F17/00 ,  H01F41/04 ,  H01L49/02

CPC classification number: H01F27/29 ,  H01F17/0013 ,  H01F41/041 ,  H01L28/10 ,  H01F2017/0073

Abstract: Disclosed is apparatus including a vertical spiral inductor. The vertical spiral inductor may include a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers, a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers separates each of the plurality of dielectric layers. A first spiral coil is arranged in a first plane perpendicular to the substrate, where the first spiral coil is formed of first portions of the plurality of conductive layers and a first set of vias of a plurality of vias, configured to connect the first portions of the plurality of conductive layers.

公开(公告)号：US20240234418A9

公开(公告)日：2024-07-11

申请号：US18047954

申请日：2022-10-19

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Haining Yang

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical transport field effect transistor (VTFET) comprising: a plurality of FET structures on a substrate; the plurality of FET structures comprising: a first n-type FET structure oriented in a first plane direction relative to the substrate; and a first p-type FET structure oriented in a second plane direction relative to the substrate; wherein the first n-type FET structure and the first p-type FET structure each comprises a FIN having a FIN height, H, wherein H defines the FIN height orthogonal to a surface of the substrate, each FIN being configured to transport charge carriers orthogonal to the surface of the substrate along the FIN height.

公开(公告)号：US20240136357A1

公开(公告)日：2024-04-25

申请号：US18047954

申请日：2022-10-18

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Haining Yang

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical transport field effect transistor (VTFET) comprising: a plurality of FET structures on a substrate; the plurality of FET structures comprising: a first n-type FET structure oriented in a first plane direction relative to the substrate; and a first p-type FET structure oriented in a second plane direction relative to the substrate; wherein the first n-type FET structure and the first p-type FET structure each comprises a FIN having a FIN height, H, wherein H defines the FIN height orthogonal to a surface of the substrate, each FIN being configured to transport charge carriers orthogonal to the surface of the substrate along the FIN height.

公开(公告)号：US20240021586A1

公开(公告)日：2024-01-18

申请号：US17812300

申请日：2022-07-13

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: H01L25/07 ,  H01L25/00

CPC classification number: H01L25/074 ,  H01L25/50 ,  H01L24/80

Abstract: A stacked gate-all-around (GAA) complementary field-effect transistor (CFET) includes a first GAA FET of a first type and a second GAA FET of a second type. Each of the first GAA FET and the second GAA ITT includes at least one three-dimensional (3D) semiconductor slab with a channel region and a first surface. A first gate structure surrounds the channel region in the first GAA FET, and a second gate structure surrounds the channel region in the second GAA FET. The first gate structure is stacked opposite the second gate structure in a direction orthogonal to the first surface. In some examples, a first crystal structure of the 3D semiconductor slab in the first GAA FET has a first orientation, and a second crystal structure of the 3D semiconductor slab in the second GAA FET has a different orientation for improved carrier mobility.

公开(公告)号：US11744059B2

公开(公告)日：2023-08-29

申请号：US16712063

申请日：2019-12-12

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Haining Yang ,  Bin Yang

IPC: H10B10/00 ,  H01L29/66 ,  G11C11/412 ,  H01L29/78 ,  H01L27/02

CPC classification number: H10B10/12 ,  G11C11/412 ,  H01L27/0207 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Certain aspects are directed to a static random access memory (SRAM) including an SRAM cell with a pass-gate (PG) transistor having increased threshold voltage to improve the read margin of the SRAM cell. The SRAM generally includes a first SRAM cell having a pull-down (PD) transistor and a PG transistor coupled to the PD transistor. In certain aspects, the SRAM includes a second SRAM cell, the second SRAM cell being adjacent to the first SRAM cell and having a PD transistor and a PG transistor coupled to the PD transistor of the second SRAM cell. The SRAM may also include a gate contact region coupled to a gate region of the PG transistor of the first SRAM cell, wherein at least a portion of the gate contact region is offset from a midpoint between the first SRAM cell and the second SRAM cell.